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Article #601Re: Intel 486 on-chip cache in a multiprocessor config ?
From: Michael Davidson
Date: Wed, 09 Sep 1992 18:40
Date: Wed, 09 Sep 1992 18:40
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adykes@jpradley.jpr.com (Al Dykes) writes: >Can the 486 on-chip cache maintain cache coherency in >a shared memory MP configuration ? Yes - see the 486 hardware reference manual for details of how internal cache invalidation bus cycles work. (btw this doesn't just apply to MP systems - the same technique is used to maintain coherency of the internal cache when any other bus master device modifies the contents of memory)
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Newsgroups: comp.sys.intel Path: arc1-ca.pugleaf.net!sparky!uunet!scorn!scolex!md From: md@sco.COM (Michael Davidson) Subject: Re: Intel 486 on-chip cache in a multiprocessor config ? Organization: The Santa Cruz Operation, Inc. Date: Wed, 09 Sep 1992 18:40:23 GMT Message-ID: <1992Sep09.184023.28664@sco.COM> References: <1992Aug31.170710.7898@jpradley.jpr.com> Sender: news@sco.COM (Account for Usenet System) Lines: 12