🚀 go-pugleaf

>>...and dumps everytime it loads.  Can anyone confirm the pipeline bug
>>in the 80386DX processor version SX211 and explain just what instruction
>>pipelining is ? ...
>
    >This sounds very unreasonable to me.  Instruction pipelining refers
>to overlapping the execution of several instructions as they pass through
>different functional units of the chip.  So, for example, while one

Various versions of the 386 have different assortments of bugs; at least
one version had a problem with _bus_ pipelining, which is entirely
separate from instruction pipelining.  There may well be other bugs that
are associated with the instruction pipeline.

The first chips marked DX were (by coincidence) the D-step revision of the
masks.  Starting in mid-89, Intel began shipping these parts; they were
the first to use the 1-micron process, and the first to have good yield at
33 MHz. Unfortunately, they also had a new, serious bug.

Under just the right conditions, including instruction decode queue full,
paging enabled, instructions fetched using pipelined bus cycles, and then
a TLB miss, the prefetch queue is corrupted. This is obviously
catastrophic, should the proper set of conditions exist.

The only condition that can be readily avoided is to not use pipelined bus
mode. This bus mode is designed to allow more access time when using DRAM-
only systems, but is not used in systems with caches. This makes the bug
harmless for the majority of systems.

So, this long-winded answer may or may not apply to the problem that
began this thread. I don't know when Intel fixed the problem, or even
if they fixed it. In 1989, they continued to ship older 1.5-micron process
parts to 20- and 25-MHz customers that used pipelined bus mode.

Can anyone at Intel fill us in on the 386 revision history and markings?

Michael Slater, Microprocessor Report   mslater@cup.portal.com
874 Gravenstein Hwy. So., Suite 14, Sebastopol, CA 95472
707/823-4004   fax: 707/823-0504