🚀 go-pugleaf

     I am using a UPI-452 in a project and am having trouble with 
the host communications. The device seems to lose the correct 
status information occationally. The bus access cycle time is not 
being comprimised, ie: 12 MHz crystal on the '452 gives a min bus 
cycle time of 500 ns, the host is an 8MHz V40 with 3 wait-states 
on the I/O channel (875 ns min I/O cycle time).

     When I load the output FIFO with a DSC followed by a data 
byte, I am able to read the device reliably when single stepping 
the host software. When I run the host full speed, the HSTAT 
register is read incorrectly. It tends to remain 0xF8. If I 
"manually" read the FIFO (either DSC or data), I get the correct 
values! (According to the manuals, if the status says there is no 
bytes in the FIFO, the values read should be 0xFF not the correct 
data!!!) I have both the IFRS and OFRS bit set to interrupt on 
"not empty" or "not full" instead of the default full and empty.

     This only seems to happen when I have a DSC followed by a 
FIFO data value, if I load the FIFO with data only, all seems to 
work correctly.

     I am confused. Anybody out there a wizard with the '452? If 
so could you help me with some code fragments (with comments) of 
both the host and '452 communications protocols.

     Intel Canada's comments were "Boy, that is not a very popular 
part!" Admittedly, he was a sales engineer not an app eng. 

                                  Neil Hamilton

Oceanography Dept, Dalhousie University, Halifax, NS B3H 4J1
(902)494-3638
neil@ocean.papa.dal.ca