Article View: comp.sys.intel
Article #828<None>
From: Steven A. Moyer
Date: Wed, 19 Dec 1990 19:07
Date: Wed, 19 Dec 1990 19:07
21 lines
1629 bytes
1629 bytes
I'm looking for information concerning how cache lines are filled on the i860 processor. In particular, does the i860 make use of the NA# signal (assuming it is support by the memory subsystem) in order to pipeline cache line reads? In measuring load rates on an RX node, I can obtain a rate of 20M/sec using the pfld instruction. With the cache flushed so that there is no write-back, I can only obtain a rate of 10M/sec using the fld instruction. Yet, the hardware reference manual seems to imply that the cache controler does indeed take advantage of memory pipelining when available. Any ideas? +--------------------------------------------------------------------+ | Steven Moyer | THIS SPACE FOR RENT | | University of Virginia | | | | "Just a rebel without a clue..." | | E-mail: sam2y@virginia.edu | - The Replacements | +--------------------------------------------------------------------+
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Path: arc1-ca.pugleaf.net!utzoo!attcan!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!ns-mx!iowasp.physics.uiowa.edu!maverick.ksu.ksu.edu!zaphod.mps.ohio-state.edu!sdd.hp.com!elroy.jpl.nasa.gov!ames!haven!uvaarpa!murdoch!batik.cs.Virginia.EDU!sam2y From: sam2y@batik.cs.Virginia.EDU (Steven A. Moyer) Newsgroups: comp.sys.intel Subject: <None> Message-ID: <1990Dec19.190753.16496@murdoch.acc.Virginia.EDU> Date: 19 Dec 90 19:07:53 GMT Sender: news@murdoch.acc.Virginia.EDU Reply-To: sam2y@batik.cs.Virginia.EDU (Steven A. Moyer) Organization: University of Virginia Lines: 21