Article View: comp.sys.intel
Article #9Re: Caching on Intel Chips
From: Stephen R. Phillips
Date: Thu, 22 Oct 1992 05:46
Date: Thu, 22 Oct 1992 05:46
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Thier I860 chipset uses seperate chaches. They may have a problem with the using I and D caches since with a CISC processor thing get more convoluted :) Cyberman/Stephen
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Path: arc1-ca.pugleaf.net!sparky!uunet!charon.amdahl.com!pacbell.com!iggy.GW.Vitalink.COM!cs.widener.edu!hela.iti.org!usc!zaphod.mps.ohio-state.edu!swrinde!gatech!rutgers!ub!exucom.com!cyberman From: cyberman@exucom.com (Stephen R. Phillips) Newsgroups: comp.sys.intel Subject: Re: Caching on Intel Chips Message-ID: <1992Oct22.054643.27802@exucom.com> Date: 22 Oct 92 05:46:43 GMT References: <1992Oct21.175835.2971@cs.mcgill.ca> Organization: ExuCom MultiMedia Inc. Lines: 5 X-Newsreader: TIN [version 1.1 PL6]