🚀 go-pugleaf

From the discussion of installing 100 & 120ns SIMMs on MacIIs, I conclude 
that at 16Mhz, the memory access is 1 wait state.  Is this correct?  Is
this forced by the bus architecture, or is it just to keep the memory
price down?  If you used 80ns memory (assuming such could be had for less 
than the national debt), could coprocessors on other boards get to the 
memory with zero wait states?

It's amazing what a difference this makes.  When forced to use an MS-DOS
machine, I use a 10Mhz 80286 machine with 100ns 0 wait state memory.  This
has been benched out at only 15-20% slower than 80386 16Mhz 1 wait state
machines.

I suspect this is why Motorola is moving so heavily into on-chip cache 
structures;  Clearly, the bottleneck on current microprocessors is not 
their speed, but the bandwidth to memory!

Also, given that I like my Mac, but I am frequently forced into MS-DOS by
business considerations,  what is the structure of the AST coprocessor 
boards?  Do they have their own, on-board memory, or do they share the
Mac's?  In either case, what is their clock speed, and how many wait 
states to memory?  Frequently, in the Intel world, the math coprocessor
is run at a different speed than the main chip. Do these add-on boards
support intel coprocessors, and if so, what speed do they run at.

Is that enough questions?

E-mail me your answers, and requests for summaries.  I will E-mail or 
post as demand warrants.

Thanks in advance...
                              Dan Graifer
                              graifer@net1.UCSD.EDU
Disclaimer: Nobody ever listens to me anyways; Why should they start now?