🚀 go-pugleaf

In article <6453@apple.UUCP> north@apple.UUCP (Donald N. North) writes:
>For the record, the HMMU (an Apple custom, not a 68461) adds ONE wait state
>to each basic memory access; when it is replaced with a PMMU (68851) TWO wait
>states are added to each memory access.  Thus it only pays to use the 68851
>when you really need it (ie, for A/UX).  It not only costs you $$ but degrades
>performance too.
>
>Don North
>Apple Computer, Inc.
>Advanced Technology Group

The March APDA draft of "Macintosh Family Hardware Reference" states,
on page 149, that "With either the PMMU or HMMU, one additional wait
state is imposed to do address translation.  Remember that there is
one wait state for the ROM and RAM accesses because of the basic
hardware timing (4 clock cycles for memory access), thereby making
ROM and RAM accesses take a total of 5 clock cycles."

Is it wrong?  Wouldn't be the first time...

Stew Rubenstein
Cambridge Scientific Computing, Inc.
UUCPnet:    seismo!harvard!rubenstein            CompuServe: 76525,421
Internet:   rubenstein@harvard.harvard.edu       MCIMail:    CSC