Article View: comp.sys.mac
Article #20380Re: Parity on Apple memories
From: Oliver Steele
Date: Thu, 15 Oct 1987 23:11
Date: Thu, 15 Oct 1987 23:11
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saf@moss.ATT.COM writes:
>Has anyone noticed that most SIMMs have 8 chips and a very few have 9? The
>obvious implication is that Apple doesn't believe in parity as a means for
>detecting errors. It would seem that particularly with 1 megabit DRAMS, the
>probability of soft errors will start to become significant. If the Macs are
>targetted at commercial users as well as the home market, then some
>robustness ought to be designed in.
Keep in mind that the circuitry for parity error detection is more
complicated, and, of course, requires a higher chip count. This means
that your system may detect errors more frequently, but that it will be
more error prone as well. As long as your memory problems aren't
intermittent a single test at boot time works better, and this is exactly
what Apple has.
(This should spark some debate :-)
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Oliver Steele ...!{decvax,ihnp4}!mcnc!unc!steele
steele%unc@mcnc.org
"'As it were' means 'I think that I sound very erudite.'
'Per se' is Latin for 'as it were.' As it were."
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Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: arc1-ca.pugleaf.net!utzoo!mnetor!uunet!husc6!rutgers!mcnc!unc!steele From: steele@unc.cs.unc.edu (Oliver Steele) Newsgroups: comp.sys.mac Subject: Re: Parity on Apple memories Message-ID: <1650@unc.cs.unc.edu> Date: Thu, 15-Oct-87 19:11:39 EDT Article-I.D.: unc.1650 Posted: Thu Oct 15 19:11:39 1987 Date-Received: Sat, 17-Oct-87 10:08:33 EDT References: <15260@clyde.ATT.COM> Reply-To: steele@unc.UUCP (Oliver Steele) Organization: University of North Carolina, Chapel Hill Lines: 23