🚀 go-pugleaf

In article <70755@ti-csl.csc.ti.com>, holland@m2.csc.ti.com (Fred Hollander) writes:
> In article billkatt@caen.engin.umich.edu (billkatt) writes:
>>language, and RISC chips are optimized for C.
> 
> This is very interesting.  I don't have the strongest background in
> hardware architecture, but, could you please explain how a processor
> could be optimized for a specific high level language?
> 
> Fred Hollander

I don't have a background either, but how about the Novix Fourth processor?
The debate might be high-levelness of Fourth. Also I have been told that a
Nat Semi proc (the "32000" I think) was like "writing in Pascal".

Saying that RISC chips are optimised for any high level language sounds
contradictory (sp?) to me. The idea is to provide very low level instructions
that the raw hardware finds easy to execute. Although compiler writers may
find it easier to write for RISC chips, a processor that supported
high(er) level intructions would have to be described as CISC (Complex 
Instruction Set Computer).

Some EE processor guru may like to correct me on some points, though :-).

Darko Volaric,
Dvorak Computer.