Article View: comp.sys.mac
Article #46318Re: 68040
From: Chrome Cboy
Date: Thu, 15 Feb 1990 16:55
Date: Thu, 15 Feb 1990 16:55
21 lines
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1539 bytes
In article <5378@okstate.UUCP> minich@a.cs.okstate.edu (MINICH ROBERT JOHN) writes: >+ The problem with these fancy new RISC machines is that they operate at such > high clock rates, the design of a cache system to keep them feed is one of > the hardest (if not THE hardest) parts to getting the things to exploit the > full capabilities of the CPU. When a RISC machine doesn't get memory when it > wants it, it has to hold up an entire pipeline of instructions to do it, and > consequently clobbers effective performance. I just read in the Wednesday edition of the Minneapolis Star Tribune that IBM has finally started production line testing of their new 16 meg SIMMs. The nice thing about them is that they already are running at 50ns, and I suppose that after IBM gets all the bugs worked out, 50ns will be the slowest of the 16 meg SIMMs. This certainly should keep those RISC chips happy, huh? Just FYI... -CCb f d d r :-)
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<11291@thor.acc.stolaf.edu>Path:
arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!usc!zaphod.mps.ohio-state.edu!uakari.primate.wisc.edu!nic.MR.NET!thor.acc.stolaf.edu!agnes.acc.stolaf.edu!sobiloffReferences:
<5221@ur-cc.UUCP> <5378@okstate.UUCP>Show Full Headers
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!usc!zaphod.mps.ohio-state.edu!uakari.primate.wisc.edu!nic.MR.NET!thor.acc.stolaf.edu!agnes.acc.stolaf.edu!sobiloff From: sobiloff@agnes.acc.stolaf.edu (Chrome Cboy) Newsgroups: comp.sys.mac Subject: Re: 68040 Summary: Actually info on fast RAM Message-ID: <11291@thor.acc.stolaf.edu> Date: 15 Feb 90 16:55:26 GMT References: <5221@ur-cc.UUCP> <5378@okstate.UUCP> Sender: news@thor.acc.stolaf.edu Reply-To: sobiloff@agnes.stolaf.edu (Chrome Cboy) Organization: St. Olaf College, Northfield, MN Lines: 21