🚀 go-pugleaf

In article <10730@phoenix.Princeton.EDU> jklee@phoenix.Princeton.EDU (James Kin Wah Lee) writes:
>A little while back, someone posted a question regarding the
>RAM chips in the IIci.  More recently in MacWeek, they mention that
>the IIci contains "special, 80 nanosecond, fast page mode" RAM
>chips.  I have been following the news but I have not seen any
>postings regarding these chips.
>
>What are "fast page mode" SIMMs and how are they different from
>"normal" SIMMs?  Is one obligated to use only these special SIMMs
>in the IIci?  More importantly, can one
>obtain these from the vendors who advertise in MacWeek for
>the same prices as "normal" SIMMs???
>

(1)  You can use 80ns "regular" SIMMs, *BUT* at room temperature they may
work only for a while, almost certainly failing eventually as the Mac 
warmed up.  It's similar to using slower RAM in general.  Since there is often
considerable margin in the RAM spec, they may actually present valid data in 
time, but aren't likely to work across the full temperature range.

So...you may be able to get 80ns "regular" SIMMs to work for a while, but it
is highly unlikely they will continue to work while in your machine.  One other
note: at our local electronics shops (Fry's), almost all of the 1meg 80ns
SIMMs sold ARE fast-page mode...its pretty hard to find 80ns "regular" SIMMs.

(2) As I understand it, a 1 meg chip only has 10 address lines, but you need
20 bits to address the full 1 meg.  So what you do (for a read) is to put the
low 10 bits of the address on the address lines, and strobe the CAS line.  You
then but the upper 10 bits of the address on the address lines, and strobe the
RAS line.  Now you have given the chip the "full" address, and it will output
the data you want.   For a "regular" chip, you must do this (CAS-RAS) to read 
each piece of data.  A fast page mode chip, however, doesn't have to do this
full cycle each time.  You need to start off the same CAS-RAS cycle the same 
way, but the next 3 reads you do, all you need to do is to put the upper
10 bits of data address on the address lines, and strobe the RAS line (this,
of course, means you have to be reading datum that have their lower 10 bits
of addresses the same).  Thus you need 4 operations to get the 1st piece out, 
but only 2 operations (putting data on address lines, strobe CAS) to read the 
next three pieces of data.

The reason I gave the "read" example is that the 68030 (which the IIci uses) 
only suppports burst reads, not writes.  It does 4 longword burst reads to load
the cache line.  Without burst mode, (using the data cache) it would require 5
cycles for every read.  With burst mode, it can read the first longword in 5 
clock cycles, and the other 3 longwords in that quad-longword-aligned block in 
2 clock cycles each, to fill the cache line (hence 5/2/2/2 bursting).

Hope this was the info you wanted (and its not too long-winded).

        Mark