🚀 go-pugleaf

In <0xe23@deimos.cis.ksu.edu> paryavi@harris.cis.ksu.edu (Saiid Paryavi):
> Does anyone know what the difference between parity and non-parity RAM is in
> the Mac IIci?  Does it have to do with the speed of the RAM?  Does one type
> run faster than the other or is it that one is more reliable???

	Parity is a scheme used for detecting memory errors.  It can take
many forms, but the basic idea is that for each 8-bit byte, you actually
store 9 bits in the memory.  Everytime you write a byte (or word, or
whatever the appropriate memory transfer unit is) to memory, the hardware
counts the number of ones in the 8 data bits and makes the 9th bit (the
parity bit) either a one or a zero such that the total number of ones in
the 9 bits is even (or, depending on the machine, odd; it doesn't really
matter as long as it's consistant).

	Whenever a byte is read from memory, the hardware again counts the
number of ones in the 8 data bits, calculates what the parity bit should
have been, and checks to make sure it really is that.  If it's not, that
means a bit was either turned from a one to a zero or from a zero to a one,
either case meaning a memory error.  The hardware then signals a parity
error and presumably the operating system does something about it, often
simply just printing an error message and halting.

	To get back to your questions, it has nothing to do with the speed
of the ram chips.  The disadvantages of parity memory are that it takes
more chips (9/8ths as many in the common case described above) and the
memory system as a whole will probably be slower, even if the ram chips
themselves are the same speed, because of the added parity generation and
checking required.  This speed delay is generally pretty marginal.  If
you've ever looked at a typical Mac SIMM, you will notice that there are 8
chips and a space on the board for a ninth.  That's for the chip which will
hold the parity bits.

	With simple parity, there is no way to know which bit has the error
in it, nor is there any way to correct the error on-the-fly.  There are
more complicated parity-like schemes, called Error Correcting Codes (ECC)
which not only let you detect errors, but lets you track down exactly which
bit within the word was bad, and lets the memory system correct it before
the CPU gets the data.  These take even more memory chips (typically
something like an extra 7 bits for every 32), and incur an even greater
memory speed delay.  Larger systems usually have ECC memory.
-- 
Roy Smith, Public Health Research Institute
455 First Avenue, New York, NY 10016
{att,philabs,cmcl2,rutgers,hombre}!phri!roy -or- roy@alanine.phri.nyu.edu
"The connector is the network"