🚀 go-pugleaf

In article <1146@csuchico.EDU> fenris@csuchico.UUCP (Chris Anderson) writes:
>My company is planning on purchasing a large computer system
>next year, and I'd like to get some info on Unisys.
>
>We're specifically looking at their 7000/5x series to replace
>our current Plexus P-60's and P-95.  What I'm interested in is
>throughput, hardware reliability, customer support(!), and
>expandability.  Any information on SysV compatibility would be
>nice as well.
>
>Has anybody used this particular series?  What was your inpressions
>of the company, their support, and their hardware?  Any information
>you can give me would be very much appreciated!
>
>Of course, I'll post a summary to the net early next year, ASAP!
>
>Thanks in advance!
>
>-- Chris Anderson		UUCP: ihnp4!csun!csuchico!fenris
>   QMA, Inc.

Well I feel it's time to provide a few tips for all of you future CCI/UNISYS
customers. I do have answers to most all of your questions, but I should point
out that I have worked for both CCI and Unisys in the past ( CCI - 4 years,
Unisys - 3 years) so I do feel I have the past experience to speak on. I did
leave, I wanted a company that eas dedicated to U*ix, not one that does it in
addition to their mainframe business.

Back when Computer Consoles came out with the 6/32, it was "THE" fastest
super-mini on the market. It originally came only with 4.2 BSD O/S and was
limited to 8mb of memory, and CDC'S 160-340 disk drives.

Within a few months the 6/32 was OEM'ED to both Unisys (7000/30, 7000/40), and
to Harris (HCX-7). The development at CCI turned to another product, and
the 6/32 was left to "joust" with all of the other manufactures all alone.

Since the origional 6/32 several stop-gap systems have followed, all based
on the 6/32 (7.7 MIP machine- by CCI's own account). CCI introduced the
6/32-e, 6/32-sx, 6/32-mp, and a few other versions that made little or no
impact in the market. Unisys, as like other OEM'ers followed CCI's foot-
steps and did'nt try to enhance the 7000 series ( via hardware or software).
Don't get me wrong here, they did introduce new 515 MB disk drives (CDC) and
a new tape drive (Kennedy) and 32-bit tape controller. But for the long run
they are not counting on the 7000 series to be a strong contender, the viewpointat Unisys is "We do not want to support any proprietary 32-bit architectures",
well this leaves the 2901 bit slice cpu from CCI out in the cold. 


     SUPPORT -
              All software support comes from an 800 "hot line" in
              Blue Bell,PA. This location is far from the R/D people
              in Salt Lake City,UT. On the average you may have 1 (one)
              person on the hot line that knows how to spell 7000/XX.
              Response time (not including the initial call for help) to
              talk to a systems analyst is about 2-4 hours, that's the
              good part, the bad news is they do not have the required
              training to properly support you. So after you wait for a
              return call, then you must wait for the 800 person to send
              a question to R&D in SLC, this goes over an 1100 mainframe.
              One a day the R&D people "look" at this que of problems and
              attempt to provide answers back over the same 1100 to PA,
              then they will return your call.
            
              If you are looking for an immediate response, you are out of
              luck.

      HARDWARE -
              The 7000 series has a poor record when it comes to system
              uptime. A while back CDC and unisys had to replace every
              single 515 MB HDA assy. in the U.S.A. we are not talking
              1 or 2, it's in the thousands.

              When it comes to expansion, the 7000 series is limited,
              I'll list it below:

                  MODEL          MIPS      MEMORY   DISK     TAPE
                                 CLAIMED   MB       GB
                  ----------------------------------------------------
                  7000/40         7.7       32      16       8 (6250)
                  7000/50         5.0       32      16       8
                  7000/51         7.7       32      16       8
                  7000/52        15.0       32      16       8
           
              The 7000/40 (6/32) is the same as 7000/51 (identical 
              system performance, hardware diffs are, additional cpu
              card cage, and new power supply).
              You can only have 2 tape controllers on the system, this limits
              you to 8 tape drives, yes I know what you are saying I'll
              never use 8 drives, I know you won't, the current tape controller
              I/O throughput will not sustain "streaming mode" with ONE drive
              mutch less than 4 per controller.


    PERFORMANCE
              The current O/S that Unisys delivers (2.21.02) is based
              on a master/slave theory. They claim 15 MIPS from a dual
              cpu (7.7 x 7.7 = 15?), sure thing..... What happens when
              the slave cpu needs to do a write to disk? it interrups
              the master to do the work... thats right only the master
              can execute kernel mode calls....The more realistic speed
              rating for the 7000/52 is 1.38 x N, where is is the speed
              of a single cpu.
              Unisys/CCI claims this is a system that can support up to
              512 RS-232 ports, sure thing, just don't plug anything
              into them.
              I will list some of the common benchmark results for the
              6/32-7000 series below:
  
              Drystone                   7500 No Regsisters   7800 with
              Linpack                    .96 MF- single pre.  .47 double
              AIM  II- III            sorry, call Aim .
              NNA                     sorry, call Neil Nelson

              Benchmarking is the only way to go if you are looking at a
              new computer system, pick a benchmark that gives a good
              example of your day-to-day activities, not just a program
              to copy a 1024k block from disk 1000 times. there's a
              good BM that has been posted on the net "MUSBUS" that allows
              you to create a multi-user benchmark, of your daily sysem
              mix (eg word processing, C program development, Dbase
              updates/inquires).This BM can be run on most standard 
              versions of U*ix 4.X, V7, 5.X, allowing a comparrison to
              be made based on how each system performs, not on marketing
              bs.
 
     INFO -
              I have included some text below on the general 7000 system,
              it's common info found in marketing brochures, not anything
              that's confidential.

----------------------------------------------------------------------------

        Key aspects of the 7000/xx hardware design that agument the system's
        processing speed are sumarized below.

        - Independent processing for instruction decoding, address
          generation, and instruction execution. This design enables
          the CPU to process three instructions simultaneously.

        - Parallel processing of instructions by each CPU and its
          Floating Point Processor (FPP) in a dual processor system.

        - Simultaneous processing by the master and slave in a dual
          processor system.

        - Unique method of decoding instructions.

        - High-speed cache used in virtual-to-physical address
          translation.

        - Separate cache structures for addresses, code, and data.

        - 32-bit data and address path.

        - One bus to handle the I/O stream and a separate bus for
          memory interchanges.
--------------------------------------------------------------------------

CENTRAL PROCESSOR BOARDS


        Each central processing unit (CPU), which is a five-board set,
        may have a float pointing processor (FPP), which is a two-board
        set. A dual-CPU system has two CPU sets, one or two FPP sets,
        and a clock board. A single-CPU system has one CPU set, and
        a clock board.


                      Instruction Processor   (IP)
                      Control Unit            (CT)
                      Dual Address Translator (DAT)
                      Address Generator       (AG)
                      Dual Data Loop          (DDL)

                      Dual Clock Board        (DCLK)

                      Floating Point Sum      (FS)
                      Floating Point Multiply (FM)


        BOARD DESCRIPTION

        Instruction Processor (IP)  

                The Instruction Processor fetches machine instructions,
                also called macro-instruction, from main memory. It 
                decodes the instructions and stores them in a large
                instruction cache. Instructions are transfered from the
                cache one at a time form processing ( 4k longwords).
              

        Control Unit          (CT)    

                The Control unit effectively translates each macro
                -instruction into a series of equivalent micro-instructions
                that direct the actual execution of the macro-instruction.
                The entire set of micro-instructions is stored on the
                Control Unit in the control store. (WCS)

        Address Generastor    (AG)      

                The Address Generator creates a "next cache-address" which
                refers to the next logical location to be addressed in the
                data cache. If the required data element is there, the AT
                 will not need to generate a memory reference.


        Address Translator    (AT) (DAT)            

                Translates the virtual addres created by the AG to a
                physical address in memory. It determines if the address
                is in cache or if a request to main memory is needed. The
                data retreived is stored in cache for future reference.
                                                              
        Data Loop             (DL) (DDL)     

                The Data Loop, which contains the Arithmetic-Logic Unit
                (ALU), performs arithmetic and logical operations on the
                following kinks of data:
        
                        - Operands supplied by the data cache

                        - Data in the general-purpose register file

                        - Literal operands from the instruction cache
                          (received from the literal bus)


        Clock Board           (CLK)     

                In a single processor system (7000/ 50,51) the Clock
                Board is plugged into the card cage where the second
                Address Translator board would reside. The DL board
                generates the system clock and terminates the memory
                bus signals. The clock board in a dual-processor system
                handles the following functions:

                        - generates clock signals to each Data Loop board,
                          which in turn provides timing for the other CPU
                          boards.

                        - grants mastership of the memory bus.


        Floating Point Processor  (FM/FS)
                

                The two-board Floating Point Processor handles instructions
                that include fractions and trignometric functions. In a
                single processor system (7000/30/40/50/51) one FPP board
                set may be used. In the dual processor (7000/52), an FPP
                may be used on each CPU.

                If the system does not have FPP hardware, then the software
                can emulate the operations of the FPP board set and execute
                floating point instructions. It is the floating point
                hardware that, without a wait state, permits execution of
                floating point instructions while the CPU is handling other


       MEMORY

        Memory Bus
                
                A special hight-speed synchronous bus connects the memory
                directly to the CPU/CPU. This memory bus is 32 bits wide
                and has a 100 nanosecond transfer time.

                In addition to data and address information, the memory
                bus has lines for the seven-bit ECC code. Generated by
                the MIB, the code is appended to each data element
                during a memory write operation. When data is read from
                memory, these bus lines contain the stored check bits.
                The check bits are transferred to the MIB, where they
                are verified by the ECC logic.


        Memory Interface Board  (MIB)
        
                The Memory Interface Board serves a variety of control
                functions, including the following:

                        - requests access to main memory for I/O system

                        - generates ECC code for write accesses

                        - detects/corrects errors in ECC codes for read

                        - refersges the memory while the system is up
                          or on battery backup.

                        - when the master CPU generates an address that
                          maps to a locatiopn in I/O space, the MIB 
                          communicates that request to the I/O subsystem.


       VERSAbus Adapter


        The VERSAbus Adapter (VA), which consists of the Memory Interface
        Board (MIB) and the VERSAbus Interface Board (VIB), functions
        as the I/O interface of the system. The VA communicates with
        the two system busses - the memory bus and the VERSAbus - to
        transfer data between the CPU and the peripheral devices.

        The Memory Interface Board controls the use of the memory bus
        by fielding requests from the CPU and the I/O subsystem.
        When the I/O subsystem initiates the request, the MIB receives
        the message from the VERSAbus Interface Board. Besides providing
        a path between the central recources and I/O, the MIB contains
        the registers used for system control and error reporting, as well
        as the ECC logic. The MIB supports a sustained burst rate of 40 MB
        per second to or from memory, detecting and checking errors at the
        same rate. All transfers to or from the MIB are 32-bits wide.

        The VERSAbus Interface Board (VIB) links the VERSAbus to the     
        centralized system recources. It receives requests from I/O
        controllers when a device is sending data, and it receives
        requests from the MIB when the CPU accesses the I/O subsystem.
        The VIB transfers single bytes, words, and longwords for
        normal I/O and direct memory access (DMA) references. It also
        supports sequential transfers by devices, in which a series of
        memory locations are read from or writen to a single starting
        address.
        
-------------------------------------------------------------------------

One final note, yes I do now work for Pyramid Technology, I am not doing this
so Pyramid can get more business, I just do not want to see you or any one
else make a BIG mistake.

And one final point of interest.... In my last few days working with Unisys
I was introduced to the new REPLACEMENT SERIES for the 7000, yes the do not
plan on keeping the line around, and after all what will happen to CCI now
they have been purchased by STC of England?


ALL of the above  is my own oppinion and in no way reflects my current
employers view point.
---------------------------------------------------------------------------
      -m-------  Jeff  Wallace
    ---mmm-----  Pyramid Technology Corporation
  -----mmmmm---  Mountain View, CA
-------mmmmmmm-  U.S.A.