🚀 go-pugleaf

In article <1aehh5INNa0r@stephen.cs.ubc.ca> sritchie@cs.ubc.ca (Stuart Ritchie) writes:
>In article <1ae4klINNpph@agate.berkeley.edu> izumi@pinoko.berkeley.edu writes:
>>My DSP gets interrupted 150,000 times per second with each sample
>>being 12 or 16 bits, and 68040 doesn't even notice this unless
>>something interesting happens in the input samples.
>
>Is the DSP fielding interrupts at this rate, or is this while polling?
>(polling is cheating)

    DSP chips are designed to handle real-time operations.  It's kinda
    useless using an 040 for this when you cannot guarentee the interrupt
    latency (and the fastest an 040 can take an interrupt is too slow
    anyway).

    DSP chips generally have very specialized interrupt hardware.  An
    interrupt on the Analog devides ADSP or Motorola 5600[0/1] for example
    fetches two instructions and INSERTS them into the instruction pipeline
    (this is known as a short interrupt).  If one of the instructions is a
    JSR then the mechanism extends into a long interrupt.

    The overhead for any DSP interrupt that utilizes the quick mechanism is
    ZERO, the minimum processing time for such interrupts being 2 cycles
    (to run the two instructions).  The overhead for a long DSP interrupt
    is generally on the order of 2 cycles (the JSR).  The interrupt
    latency, baring interrupts being disabled, is the 2 or 3 cycles it
    takes to get to the inserted instructions in the pipeline... not wasted
    either since the DSP is still executing main line code for those 2 or 3
    cycles.

    Interrupts on DSP chips can be FASTER then polling.

    This is why even a 4 MHz DSP can handle more real time IO then a 33 MHz
    040.

>It might be more flexible and easier to interface with if the "DSP"
>was the same architecture as the host processor.  Even more so if
>the host and DSP were in the same address space.

    Then it wouldn't be a DSP chip. <grin>

				    -Matt

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    Matthew Dillon		dillon@Overload.Berkeley.CA.US
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