🚀 go-pugleaf

>In article <1992Oct1.192347.17114@netcom.com> abell@netcom.com (Steven T. Abell) writes:
>>louie@sayshell.umd.edu (Louis A. Mamakos) writes:
>>> Serial ports don't have to interrupt on every character.  If there
>>> were a moderately intelligent serial controller, plus DMA support for
>>> the I/O transfers, then things could be quite zippy, thank you.
>>
>>The validity of this line of thinking depends on what you're doing.

    There are plenty of serial chips out there that take the pressure off
    the CPU that are not DMA, NeXT simply isn't using them (probably for
    cost reasons).

    For example, the signetics (now phillips) 26/68C94 is quad-uart with 8
    character transmit and 8 character receive FIFO's.  You can set the
    fill level for the receive FIFO before getting an interrupt and the
    chip has a dedicated watchdog timer for each channel to handle tail
    ends of data streams.  The chip also has a really wonderful interrupt
    subsystem.	You can do similar tricks with the transmit FIFO.  We can
    do 78.6 Kbps on one channel and 19.2 Kbps on the other three channels
    simultaniously in both directions with a 68HC000 based board running at
    10MHz.

    There really is no reason why NeXT can't go fast with their two serial
    ports, it's basically a matter of rewriting the serial interrupt to not
    go through umpteen layers of device drivers from INSIDE the interrupt,
    and to not disable processor interrupts for long periods of time in
    other parts of the kernel.

					-Matt

>Steve abell@netcom.com

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