Article View: comp.sys.next.hardware
Article #1270Re: Acorn 610 as processor/coprocessor?
From: Lars Peter Fischer
Date: Thu, 19 Nov 1992 19:18
Date: Thu, 19 Nov 1992 19:18
59 lines
3193 bytes
3193 bytes
>>>>> "Bill" == Bill Williams (bwilliam@iat.holonet.net) Bill> re : "1) I believe that the Acorn 610 has a 4k on chip cache." Bill> Yeah right! Bill> It has only 32000 transistors yet can magically support 4096 bytes of Bill> cache RAM in the 32000 transistors... Bill> [...] Bill> SOMEONE OUT THERE IS A LIAR!!!! I assume the liar is Acorn, and that the Bill> chip has 500,000 transistors and not the 32000 transistors claimed. Now, let's try to get this right: - The ARM is a CPU architecture, designed by Acorn, later sold to Advanced Risc Machines, a company owned by Olivetti, Apple, and VLSI Logic (Acorn has been taken over by Olivetti). - There has been a number of implementation of the ARM architecture developed by Acorn and manufactured by VLSI Logic (ARM 1, 2, 3). The ARM3 chip design has been handed over to Advanced Risc Machines and is the current chip used by Acorn for their Archimedes range. - ARM6 is a macro cell implementation of the ARM architecture. A macro cell is sort of a VLSI module, something you can take as a components and plug into an ASIC (Application Specific IC). It's *not* a chip, it's a chip modules. It's a complete CPU. - ARM6 has 36000 transistors. - You can call Advanced Risc Machines and order a ASIC that includes ARM6 as a component. You specify what else goes there, depending on what you need. Might be a UART or a MMU or video controller or something else. This allows Advanced Risc Machines to sell the same architecture to people that build industrial control electronics and people that build laser printers. - ARM610 is a specific chip build is this way, using the ARM6 macro cell. The ARM610 also includes a rather strange MMU that is supposed to be great for OO -- it has a protection system that is orthogonal to the paging system. I don't really understand how this works just yet -- I'll have to get more specs. The ARM610 also includes a 4 kbyte, 64 way cache. The cache is small and many-way to save power. The ARM610 is completely static and has advanced control logic that allows the clock to be changed and stopped at any state and other niceties to save power. - ARM610 does not take advantage of all ARM6 features. It does not support the coprocessor interface. - There is no such things as an Acorn 610, so I can hardly see Acorn being a liar in this matter :-) /Lars -- Lars Fischer, fischer@iesd.auc.dk | It takes an uncommon mind to think of CS Dept., Aalborg Univ., DENMARK. | these things. -- Calvin
Technical Details
Message-ID:
<FISCHER.92Nov19191840@steinhaus.iesd.auc.dk>Path:
arc1-ca.pugleaf.net!sparky!uunet!mcsun!sunic!dkuug!iesd!iesd.auc.dk!fischerReferences:
<1992Nov8.130614.19372@wam.umd.edu> <BxL7t4.3tE@iat.holonet.net>Show Full Headers
Complete Article Headers
Newsgroups: comp.sys.next.hardware Path: arc1-ca.pugleaf.net!sparky!uunet!mcsun!sunic!dkuug!iesd!iesd.auc.dk!fischer From: fischer@iesd.auc.dk (Lars Peter Fischer) Subject: Re: Acorn 610 as processor/coprocessor? In-Reply-To: bwilliam@iat.holonet.net's message of Thu, 12 Nov 1992 05:12:39 GMT Message-ID: <FISCHER.92Nov19191840@steinhaus.iesd.auc.dk> Sender: news@iesd.auc.dk (UseNet News) Organization: Mathematics and Computer Science, Aalborg University References: <1992Nov8.130614.19372@wam.umd.edu> <BxL7t4.3tE@iat.holonet.net> Date: 19 Nov 92 19:18:40 Lines: 59