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Article #974

Re: New RISC workstations / 88110 demise

#974
From: Mat Hostetter
Date: Sat, 07 Nov 1992 18:14
29 lines
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In article <1992Nov6.205045.26293@netcom.com> abell@netcom.com (Steven T.  
Abell) writes:
> songer@lexmark.com (Christopher Songer) writes:
> 
> > Intel's chips may be buggy, the instruction set may be ugly, but they
> > are fast for the price. The silicon eratta and non-orthogonal instruction 
> > set would be dealt with by people at Next. The benefits would be
> > speed and price for the users. Sounds like a good choice if they've
> > got good people. (And they do.)
> 
> Unfortunately, you can't just brush of an obnoxious architecture by saying
> "The compiler people will worry about this." Let's stay real, folks.
> Underlying models matter, and the Intel model is about as bad as they come.
> If this is what we have to live with, I suppose we'll manage somehow,
> but if you think it doesn't affect you, you're wrong.

This is true, especially if you look ahead 10 years.  While it's true that the  
P5 will be fast and cheap, it's a bad choice for the long run "high end"  
machine.  Let's face it, the architecture is inherently crippled.  If NeXT  
wants to think long term they should use a visionary architecture like DEC's  
Alpha, which was designed from scratch to be competitive (actually, 50% faster  
than the competition) for the next 20+ years.  It's clean, it's fast, and it  
will keep getting faster.  Intel will hit a brick wall with this series of  
chips, no matter how many hundreds of millions they pour into it.

The P5 may be a good choice for a LOW end machine, though, once mass production  
drops the price.

-Mat
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Path: arc1-ca.pugleaf.net!sparky!uunet!spool.mu.edu!snorkelwacker.mit.edu!bloom-picayune.mit.edu!news
References: <1992Nov6.205045.26293@netcom.com>

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From: mjhostet@athena.mit.edu (Mat Hostetter)
Subject: Re: New RISC workstations / 88110 demise
Message-ID: <1992Nov7.181432.9086@athena.mit.edu>
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Date: Sat, 7 Nov 1992 18:14:32 GMT
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