🚀 go-pugleaf

Scott Mason (mascot@bnr.ca) wrote:
: In article <1992Oct20.215652.119445@ua1ix.ua.edu> bcleve@ha05.eng.ua.edu (Brian D. Cleve) writes:
: >It was to have been announced last thursday, the 15.
: >Does any one heard about the specs or anything?
: >
: >Brian
: 
: We haven't been released from our NDA yet; however, I contacted our
: local Motorola sales office (thanx, Bela) and below is the information
: which I received. I'm afraid that I cannot attribute the source, but it
: appears to be a magazine designated only "EN". Reprinted without
: permission:
: 
: Intel P5, Motorola 68060 In MPU Forum Limelight.
: By Jonathan Cassell
: 
: Burlingame, Calif. -
: 
: Intel and Motorola engineers last week detailed the superscalar,
: pipelined architectures of the respective P5 and 68060 microprocessors
: at the annual Microprocessor Forum here.
: 
: (P5 description)
: 
: Motorola's 060 is a 32-bit processor with a superscalar, pipelined
: architecture.  It has more than 2 million transistors, using a
: 0.5-micron, triple-layer metal, 3.3 volt process in a static design.
: Performance will be 3.5 times the 25MHz 68040, or about 46 Specmarks,
: according to Joe Circello, 68000 advanced microprocessor architect for
: Motorola.
: 
: Separated in the 060 are instruction caches and data caches;
: instruction fetch pipelines (with four-stage instruction processor, a
: physically-mapped 8Kbyte instruction cache with four-way self
: associative, a virtually mapped, 256-entry branch cache and a FIFO
: instruction buffer), and operand execution pipelines (with four-stage
: operand processor, a physically mapped 8Kbyte data cache with 4-way
: interleaving and a 4-entry, 32-bit write buffer).
: 
: The floating point unit - implemented in the execution stage of the
: operand execution pipeline - is compatible with the 040 FPU programming
: model. Floating point execution times range from 1-24 cycles. The 060
: superscalar dispatch algorithm can execute 50 to 60 percent of integer
: code instructions as pairs with existing compilers.
: 
: The 060 will come in 040-style packaging, with a similar external bus.
: The first versions will sample in the second half of 1993, go into
: production in Q1 1994, and run at 50MHz and 66MHz.
: 
: --
: 
: End included material. Don't mail me. I cannot discuss the 68060 at
: this time.
: 
: ------------------------------------------------------------------------
: #include <disclaimer.h>                          Bell-Northern Research
: Scott Mason                                      P.O. Box 3511 Station C
: Internet: mascot@bnr.ca                          Ottawa, Canada, K1Y 4H7

This sounds as if it's a real boon to all of the entrenched NeXT owners out
in the marketplace.  To be able to have the packaging similar to the 68040
that's currently installed in them, it would seem that a small daughterboard
would be just about (_JUST_ about) all that's required to convert an existing
25/33MHz NeXTstations into abusing the 50/66MHz 68060 at the slower clock
speeds.  *sigh*


-- 
Dan Berry			bugs%atlantis@kakwa.ucs.ualberta.ca
==============================> bugs@atlantis.uucp  =========================
"On a first date, watch how your date treats the waiter, the bartender,
	and so on.  That's how she'll be treating YOU after three months."