🚀 go-pugleaf

In article <1992Apr17.045418.23581@athena.mit.edu> jgshir@athena.mit.edu (John G Shirlaw) writes:
>In article <1992Apr16.180415.26582@cs.ucla.edu>, esky@marathon.cs.ucla.edu (Eskandar Ensafi) writes:
>|> 
>|> Why not NeXT? I mean, Ariel has come out with PC boards using the 96001  
>|> "Multimedia" DSP chip from Motorola.
>|>   
>|> For those of you who don't know, the chip is binary-compatible with the 56001  
>|> that NeXT uses and it is called a multimedia chip because, being a 32-bit  
>|> version of the 24-bit 56001, it can process sound and graphics simultaneously.
 
Could you please site the document which says the 56001 and the 96001 are binary
compatable?  Motorola's Technical Summary of the 96001 (BR574/D, (C) 1988) says
in its opening paragraph that the two chips are "software compatable."  However,
on page 21 youll find the following:  "Because the DSP96001 floating-point data
ALU is substantially different from the DSP56001 fixed-point data ALU, serveral
assembler options are provided to allow source-code compatability across both
families."

As for its being called a Multimedia chip, I suspect it may have more to do with
the fact that the TI320C30 seems to be the chip of choice in the DSP market, Im
told due to the fact that it is far cheaper than the 96000 series.  With the
TI320C40 having very good support for building multiprocessor systems (even with its
odd 325(?)-pin zig-zag PGA arrangement :-) it may be the Motorola chip would
still not be the chip of choice for building scalable multimedia systems.  I fear
this volume/price thing will also severely hamper the evolution of the 88110
series.  Dont forget, before AMD, Intel could charge hundreds more per each
of millions of 386/486 chips.  That means potentially billions more to invest
in future growth.

>|> a 33-MHz 96002 processes 16.5 MIPS and 49 MFLOPS.  The dual 88110 CPUs being  
>|> rumored lately beat this chip in the MIPS, but do they have the MFLOPS?  I  
>|> think it would be a good idea to use it in both 040 and (if ever) 88110  
>|> systems.
>|> 
>|> What do you think?
>|> 
>|> Eskandar Ensafi --- esky@marathon.cs.ucla.edu, esky@mayhem.icsl.ucla.edu

I think advertising literature may be somewhat misleading.  49 MFLOPS is high,
considering the only instruction that will do that is FMPY//FADDSUB.S.  Im told
by a few DSP gurus that this instruction isnt used by the algorithms they work
with, giving a typical peak performance of 33 MFLOPS (if you see where this is
commonly used, please write to me!)  On the other hand, modulo and bit-reverse
address generation is required by many DSP algorithms.  The fact that address
generation occurs in parallel with the Data ALU operations means that the
MOPS/MIPS value is far higher for a DSP chip than a standard RISC chip.  The
fact that DSP systems are typically built around 0 wait state memory systems
instead of slower cached memory systems means the performance is predictable,
which is a critical factor for hard real-time systems.

>Another interesting question is why didn't NeXT replace the 56001 with the 96002
>when they introduced the new turbo's?  this should have been a simple mod given all the other
>things they have been doing to the board any way.
>
>john.

The latest rumor up the pike is that there will be no DSP with the NRW.  If the
96001 (the 96002 doesnt have the serial ports or host port) isnt fully binary
compatable it would be a big change for one generation, just to watch both
generations die.

If NeXT ever catches up to the rest of the world in desktop systems (DECs TurboChannel,
Suns SBus, Apples NuBus 90, etc...) it might be wiser in the long run to offer
a base DSPless system with a series of multimedia expansion cards.  That way
you only pay for the level of sophistication you need, and you have more options
as to how many levels there are.  Right now its just the NeXTdimension or nothing.

-Steve