Article View: comp.sys.next.misc
Article #3891New RISC chip / IMS 3250
From: Bruce Henderson
Date: Tue, 17 Nov 1992 20:59
Date: Tue, 17 Nov 1992 20:59
61 lines
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2821 bytes
OK, I can't say much about the chip because I am under non disclosure... But what I can say is this: The chip is the IMS 3250 It is made by International Meta Systems, Inc. 23842 Hawthorne Blvd, #200 Torrance, CA 90505 Phone (310) 375-4700 FAX (310) 378-7643 Some gibblies on the chip: Superscaler RISC 2 instructions per clock peak, average of 1.5 instructions per clock Average 90 raw MIPS for the 60MHz part. Emulation On chip ROM contains 3250 native microcode, 80486 microcode, and 68040 microcode. (There seems to be a lot more room on the ROM for other microcode chunks like SPARC, or custom instructions. Here's a teaser.... What if an objective-C message pass (a somewhat computationally expensive thing) was a processor level thing, and say happened in 3 clocks? Or say they microcode a lot of mach low level stuff into silicon....) Other neat items... 1) The chip is only 50,000 gates... So it is small, and can esily fit in ASIC standard cells. (What does this mean? Well, say you had one of these things that was microcode tuned for Mach, and another for Display Postscript, and say another for DMA and another for I/O. Then you build an ASIC with 4 of these cells on it and put it in a NeXT. Think of all of the grunge the CPU no longer has to deal with.....) 2) Only dissapates 1.5 Watts, that isn't much so it may be rather useful for building things like NeXT poratbles or laptops. 3) IMS seems to be interested in a cost to vendors of around $45.00 per part. (as compared to the cost of a 50MHz 486...) So for more information, contact IMS. I don't work for them, but I do believe that there are ways that this chip could be used to improve performance of NeXT hardware. (Really.... 50,000 gates and loadable microcode...) Some of you are going to ask what the SPEC marks are, and that is the kind of stuff I can't talk about.... Sorry. I tend to think if this thing as a "Nano-processor" Meaning that you write some micro instructions for the little beast that makes it perfect of some meanial job like talking to hard disks or handling VM and then you burn it into a 100 pin flat pack ASIC and it makes your life easier. Hope this helps Bruce H (not Webster) PS. If you call, tell them you heard it from me.
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Path: arc1-ca.pugleaf.net!sparky!uunet!ogicse!network.ucsd.edu!news!nosc!pages!bruce From: bruce@pages.com (Bruce Henderson) Newsgroups: comp.sys.next.misc,comp.sys.next.hardware Subject: New RISC chip / IMS 3250 Message-ID: <1992Nov17.205959.8187@pages.com> Date: 17 Nov 92 20:59:59 GMT Article-I.D.: pages.1992Nov17.205959.8187 References: <1992Nov15.192329.324@pages.com> Sender: bruce@pages.com Distribution: usa Organization: Banzai Research Institute Lines: 61