Article View: comp.sys.nsc.32k
Article #1095Re: NS32310 Vs NS32381
From: Roger Thompson
Date: Tue, 21 Apr 1987 05:42
Date: Tue, 21 Apr 1987 05:42
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In article <323@winchester.UUCP>, mash@mips.UUCP (John Mashey) writes: > > 2.) The 32381 is an active project due out of fab in > > the mid summer time frame. It is based on the 32081 > > but is done in CMOS and will operate at up to 30 MHZ....... > > up adds and multiplies. Double precision floating > > multiplies can be done in 1 usec at 30 MHZ. > Just out of curiosity, are there timings/cycle counts available for > adds, divides? [This looks like 33 cycles for a DP multiply?] Adds and subtracts are actually a little slower than multiplies. They are approx 1.4 usec. I don't have the exact numbers on divides with me, but recollection says its about 2 usec. Generally speaking, both single and double precision calculations take the same amount of time. ews up
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Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: arc1-ca.pugleaf.net!utzoo!mnetor!seismo!rutgers!ames!oliveb!pyramid!nsc!roger From: roger@nsc.nsc.com (Roger Thompson) Newsgroups: comp.sys.nsc.32k Subject: Re: NS32310 Vs NS32381 Message-ID: <4222@nsc.nsc.com> Date: Tue, 21-Apr-87 00:42:18 EST Article-I.D.: nsc.4222 Posted: Tue Apr 21 00:42:18 1987 Date-Received: Wed, 22-Apr-87 01:38:57 EST References: <145@unsvax.UUCP> <4221@nsc.nsc.com> <323@winchester.UUCP> Organization: National Semiconductor, Sunnyvale Lines: 17