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Article #173

Re: Pseudo dma.

#173
From: Dave Rand
Date: Mon, 31 Aug 1992 06:50
51 lines
3103 bytes
[In the message entitled "Re: Pseudo dma." on Aug 31, 14:17, DALL@hfrd.dsto.gov.au writes:]
>  > 3) The 8490 can be polled (bit 6 HA 5) to determine the true state of DRQ.
>  > A proper ISR will poll this bit, and read the last byte if required.
> 
> The chip spec says that phase mismatch doesn't reset DRQ (section 3.0)
> and it also says (section 4.11.2) that the easi will stop driving the
> bus on a phase mismatch. It doesn't say that the situation arises, but
> I suppose that DRQ active means there is still a byte in the 8490 chip
> to be read. It is hard to see how this could arise on a write (if the
> scsi bus is already "not being driven" sending more data from the CPU
> to the 8490 can't do much good. Should that final read be done with
> EOP?

Yes, on a read, if DRQ (bit 6 HA 5) is set, there is a byte to be read
latched in the chip. Perhaps not on the bus, but it is on the chip. There
is no need on reads to do the EOP. On writes, it is *possible* that the
phase change occurs while you are loading the byte to be transmitted, but
then DRQ will not be asserted, and you know. If DRQ is asserted while writing,
there is no byte in the chip (unless at EOP).

>  > Again, for writes you could over-estimate if you use MOVD. If you use MOVB,
>  > and poll the DRQ bit, you *know* how many bytes were transferred.
> 
> How does this work? What I am concerned about is not the normal
> end-of-dma, which the enhanced mode seems to signal correctly, but the
> abnormal end-of-dma due to phase change etc.

See above. You will get a phase change interrupt, and there may or may not
be a byte in the 8490. Between the PC, the current count, and the DRQ bit,
you can calculate how many bytes have been transmitted.


> Also, do you recommend movb's or movd's? I am not sure if there is an
> appreciable difference in speed when the source or destination
> operands are the pseudo-dma buffer. I am getting 4.25 MB/sec using a
> loop of 32 movb's (DRAM to DRAM). I am sure a loop of movd's would go
> faster DRAM to DRAM, but since 4MB per sec nearly saturates a normal 8
> bit SCSI bus anyway, is there any benefit in going to movd's?  On the
> other hand, if the byte count is to be uncertain anyway due to the
> factors discussed, I suppose there is not much *disadvantage* in going
> to movd's.

MOVB's are OK, but there is slightly better bus utilization when doing
MOVD's. The refresh has better time to get in.

Good luck, and holler if you run into more troubles.


-- 
Dave Rand
{pyramid|mips|bct|vsi1}!daver!dlr	Internet: dlr@daver.bungi.com
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From: dlr@DAVER.BUNGI.COM (Dave Rand)
Newsgroups: comp.sys.nsc.32k
Subject: Re: Pseudo dma.
Message-ID: <m0mP5ae-0000DMC@daver.bungi.com>
Date: 31 Aug 92 06:50:20 GMT
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