🚀 go-pugleaf

In <Pine.SUN.3.91.950821100405.5161B-100000-100000@spad.eng.auburn.edu> "Jeffery D. Walker" <walkej2@eng.auburn.edu> writes:

>The MAJOR slowdown for a computer is NOT the cpu speed or the clock 
>speed, but the BUS SPEED!!!  If someone dissagres with me, try taking a 
>few computer engineering/electrical engineering courses and come back and 
>we will talk.

Maybe you should follow your own advice.  The speed of the external bus
is only one factor, amongst many others, affecting the speed of a
processor.  This is why doubling the size of the data bus (while keeping
all the others factors constant) doesn't double the speed of the cpu and
halving it doesn't half the cpu speed.  Is it that difficult to get a
clue before posting?

>this is why a 8088 is NOT considered a 16 bit machine, even though it 

This is why _you_ don't consider an 8088 to be a 16-bit cpu (it's by no
means a machine).  Your opinion is highly irrelevant.

>has 16bit registers.  a 8086 is a 16 bit machine, ONLY because it has a 
                       ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>16 bit bus, no other reason; and it is this reason that makes it that 
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>much better. 
 ^^^^^^^^^^^
Bullshit.  Please quote some hard data, showing how much faster an 8086
is than an 8088 running at the same clock speed.

>This is also why a 100MHz-486DX-4 is slower (on average) 
>than even a 75MHz P5. the bus speed/width.(among other things)

If you stay within the L1 cache, the external bus width doesn't make
any difference.  And by your brain dead definition, the 386SX is a
16-bit chip and the Pentium is a 64-bit chip.  Do you _really_ believe
this crap?

The bitness of an architecture is not defined by the size of the external
data bus, period.  

It isn't defined by the speed of the data transfers, either.  A chip
with an 8-bit data bus running at 100 MHz (and no wait states) will
transfer data faster than a chip with a 64-bit data bus running at 10
MHz.  And in both cases, the bitness will be determined by the size of
the internal data paths, the registers and the ALU.

Dan
--
Dan Pop
CERN, CN Division
Email: Dan.Pop@mail.cern.ch 
Mail:  CERN - PPE, Bat. 31 R-004, CH-1211 Geneve 23, Switzerland