🚀 go-pugleaf

In article <41ssbe$nd2@reznor.larc.nasa.gov> PJ,
pjuang@hawking.nhgs.tec.va.us writes:
>    Personally, I think they should go ahead and hit the market with a 
>"conventional" P7 - the P6 still has plenty of room for improvement - in
>late 1997, and then go ahead and wait until mid 1999 to let loose on the
>VLIW "P8" (?).   Then again, you have to take into account that AMD has
>already slated a K7 in 1999-2000 expected to reach almost 600 SpecInt.  They 
>also plan to have a K6 out to get 400 SpecInt (8 mil transistors, I think) in
>1996-97.  Seeing that the K5 has yet to be released, this is a little bit of 
>extreme farsight, don't you think?
>
Don't you love these articles from non-CPU designers?
Exactly how do you think the P6 has PLENTY of room for improvement?
They are running on a .35 micron process---improving that process is 
hitting the limits of optical lithography and the successor is not yet 
known. The pipeline has been cut to as small as it can be to ramp up the 
clock rate to 200MHz. The multiple-branch handling and instruction 
look-ahead have been pushed as far as one can reasonably go on code, 
given the burstiness of functional-unit utilization and the frequency of 
branches. They are pushing the L2 cache as hard as they can. There's 
probably no way in hell they can improve their L1 cache (say make it 
larger and go to virtually addressed) without destroying OS compatability 
(or performance). 

Maynard Handley