🚀 go-pugleaf

Maynard Handley <maynardh@apple.com> wrote:

>Don't you love these articles from non-CPU designers?

    Hmmm...if I'm not mistaken, Apple doesn't delve too heavily into
CPU design/development.  Then you would be flaming yourself, wouldn't
you?  I could be wrong, though.  I'm not an expert on another company.
    
>Exactly how do you think the P6 has PLENTY of room for improvement?
>They are running on a .35 micron process---improving that process is 
>hitting the limits of optical lithography and the successor is not yet 
>known. The pipeline has been cut to as small as it can be to ramp up the 
>clock rate to 200MHz. The multiple-branch handling and instruction 
>look-ahead have been pushed as far as one can reasonably go on code, 
>given the burstiness of functional-unit utilization and the frequency of 
>branches. They are pushing the L2 cache as hard as they can. There's 
>probably no way in hell they can improve their L1 cache (say make it 
>larger and go to virtually addressed) without destroying OS compatability 
>(or performance). 
>

     Since you won't take my word at face value, here is another article
I've got.  At least I'm reasonable enough to listen to someone at apple.com 
rattle off about Intel's P6.  Let's try to have a normalized discussion.
Let the flamers shoot themselves.

     From Byte Magazine, April 95

"There is still plenty of room for improvement in the x86 architecture. The P7 could 
be a four- to six-way superscalar machine with larger primary caches, an 
integrated secondary cache, more execution units, and larger buffers to support
deeper paths of speculative execution. It could also speculate both ways beyond a 
predicted branch, a technique IBM tried in a 1960s mainframe. "

     Now I'll be the first to admit that I'm not a CPU designer, but this seems
to me like a perfectly fine way to make an "enhanced" P6, if you will.  "Make
it bigger and better."  If I'm not mistaken, this is somewhat like the 604.  
There isn't nearly as much difference between the 604 and the 601 as there
are between the 486 and Pentium or the Pentium and the P6.  Granted, I'm not
counting the 602 and the 603.  I'm not qualified to comment on those because
I barely know anything about them.  They could even go on a multiprocessor
configuration - i.e. two chips in one, designed to work that way.  Just a filler
for the proposed VLIW project.  You know as well as I do that Intel probably has 
something to fall back on, like a P7 side project.  They won't risk everything
on an unproven technology.
     And how do you explain how Intel is trying to get the P6 up to 266 Mhz?
And aren't the first P6s going to be manufactured on a .6 process?  I
don't know much about the manufacturing processes, but Intel debuted a
Pentium 150 fairly early - around the time the DX4s were announced.  I'm
pretty sure that .35 wasn't in wide usage by that time.  They might have,
I don't know.
     Besides, who are we to say how Intel is going to improve on the P6?  I
never said for anyone to take me as Intel's PR.  My post dealt only with me
trying to second guess Intel and giving my opinion to the original poster. I
never asked for your flame.  If you've got a reasonable argument that takes 
down my theory, fine.  I readily gave up on the software translator idea when
someone else told me what goes into slapping a VLIW program together.  Leave
the flamethrower elsewhere.

"Meanwhile, Intel's competitors aren't sitting still. NexGen plans to introduce the
Nx686 by the end of this year and predicts two to four times the performance of 
the Nx586. Cyrix says it is already working on successors to the M1, though no 
details have been disclosed. 

AMD has mapped out its future in the most detail. The K5 will be followed by a K6 
in 1996, with volume production in 1997. The K6 will be fabricated on a 
0.35-micron process and is expected to have 6.5 million transistors; estimated 
performance is 300 SPECint92. In 1997, AMD plans to introduce a K7 that will ramp 
up to volume production in 1998 on a 0.18-micron process with 10 to 15 million 
transistors; it is expected to deliver 700 SPECint92 at 400 MHz. Finally, AMD is
planning a K8 in 2001 that will have 20 million transistors and deliver 1000 
SPECint92 at 600 MHz. "

      Apparently, I got my numbers mixed up in the original post.  My bad.  
But my point in case remains the same - Intel can't sit on its butt and
let someone else take too much of a lead.  In my view, they need to have
a "filler" between the P6 and the VLIW chip, if they get it worked out in
time.  The rest of the article, albeit pretty much outdated by now, is at

      http://www.byte.com