🚀 go-pugleaf

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In article <tonyn-0109950144230001@tonyn.tiac.net>,
Tony Nelson <tonyn@tiac.net> wrote:

>On any CPU, interrupt processing requires a context switch (also required
>for preemption and system services).  In the old days, this required
>simply the amount of time the CPU required to start the interrupt (and
>finish it later) plus the instructions in the interrupt handler.

a context switch is not necessary to service an interrupt; all that is
necessary is a partial context save.  many OSes service interrupts in
the kernel half of the currently running processes.  since ISRs are
not supposed to reference per-process information, the currently
running processes is irrelevant while servicing an interrupt.

most small processors use a single system-wide real memory cache
(rather than caching based on virtual address), so an interrupt
doesn't force a cache-clear, and actually if the interrupt is common
its ISR is likely to already be in the cache.  an interrupt, on most
processors, is not a mandatory cache flush.  the only case where a
context switch mandates a cache flush is when the cache is storing
virtual addresses (instead of physical).  and since a properly-written
ISR doesn't reference per-process virtual space, it's not necessary to
flush the virtual address translation cache.


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