🚀 go-pugleaf

David T. Wang wrote:
> 
> Arun Gupta (gupta@mrspock.mt.att.com) wrote:
> : David T. Wang <veakblad@Glue.umd.edu> wrote:
> 
> : [Regarding chip technology]
> : >
> : >PPC601-100 is at .35 micron.
> : >PPC604-100,120,132 is at .5 micron
> : >PPC604-150 is at .35 micron.
> 
> : Well, I'm looking at the Motorola page :
> 
> : http://www.mot.com/SPS/PowerPC/library/literature/fs/601.html
> 
> : The 100Mhz PPC601 is said to be
> : Quote
> :      * 2.5-volt implementation with 5-volt I/O
> :      * 0.5-micron static CMOS technology
> :      * 74 mm2 die size
> :      * 2.8 million transistors
> : End quote
> 
> Yes, you're right, I don't know aht I was thinking, the 66 MHz through the
> 90 MHz 601's were .6 micron, the 100 MHz was .5 micron.  However, there was
> a snippet from July 10 ,1995 issue of Microprocessor Reports, which stated
> "On the PowerPC side, only the 601 has reached the .35 micron process. IBM
> to move the 603, 604 and 620 to CMOS5X in 1H96"

The 60-90 mHz 601s were created using IBM's 0.5 micron four-metal-layer process.
The higher clocking 601s and 603s were created using IBM's 0.5 micron five-metal-
layer process.  The five-metal-layer process allowed IBM to pack more transistors
into a smaller area and increase the speed.

 
>    I believe that the .35 micron process was supposed to be on the 601+
> so whatever the 601+ is, it's supposedly manufactured on .35 micron.
> 
> (Hmm, but the Microprocessor reports may be wrong on this? the Berkley
> infopad site also seems to indicate that the 601+ is on the .5 micron
> only)

The 601+ will be using the 0.5 micron, five-metal-layer process, which is more
advanced than the 0.5 micron, four-metal-layer process as mentioned above.
 
IBM has only been using the new process on the 75(?)+mHz 603e as far as PPC are
concerned, at least to my knowledge.