🚀 go-pugleaf

David T. Wang wrote:
> 
> David T. Wang (veakblad@Glue.umd.edu) wrote:
> : Tae Song (tsong@erols.com) wrote:
> : :The 60-90 mHz 601s were created using IBM's 0.5 micron 4-metal-layer process.
> : :The higher clocking 601s and 603s were created using IBM's .5 micron 5-metal-
> : :layer process.  The five-metal-layer process allowed IBM to pack more
> : :transistors into a smaller area and increase the speed.
> 
> : This then begs the question, what exactly does IBM manufacture on its .35
> : micron process?  I recall that Intel made a big hoopla about fabbing the
> : 120 MHz Pentium on the .35 micron process back near the end of 1994, and
> : a bunch of people (including me) assumed that Intel had then surpassed
> : IBM in the process technology game and reached .35 micron first.  This
> : turned out to be incorrect. IBM later revealed that it had actually
> : fabricated some shipping chips on its .35 micron process tech (albeit a
> : relatively small quantity) about 3 month before Intel did.  Now Intel is
> : just about all converted to the .35 micron process, judging by the number
> : of 133, 15 and 166 MHz chips it's pumpimg out, but IBM seems to be still
> : manufacturing on the .5 micron process, with no move insight to move to
> : the CMOS5X .35 micron stuff until 604e.  (I still haven't found out for
> : certain what the 150 MHz 604 is fabbed on, microprocessor reports and
> : IBM's web site contracdict each other here)
> 
> Aha, I think that I've found the answer.  The answer is that IBM calls
> a couple of different process technology all as .5 micron process.
> Have a look at ...
> http://www.chips.ibm.com/technology/index.html
> 
> IBM actually has two different " 0.5 micron process technology" (okay,
> at least two, probably more) on this page it shows CMOS5L and CMOS5S.
> and if we go into more details about CMOS5L and CMOS5S, we find that
> CMOS5S has a .36 um effective channel length, and was probably the
> technology which 601 was fabbed on.  No doubt that the PPC604@150 was
> fabbed on CMOS5S, and the slower parts could be from a CMOS5L process,
> and IBM could still call them all "0.5 micron process"  This is
> probably where the confusion was introduced, as Microprocessor Reports
> may have just looked at it, and just said, okay, the 601 and the 604
> has reached .35 micron, whereas if you just looked at IBM's page without
> digging into the details, you'd think that they're all still at .5
> micron.  Maybe the CMOS5S could be described as a 0.4 micron process?
> it's defintely more advanced, and you can pack more gates onto the
> chip, as compared to CMOS5L.  This would have at least solved my confusion.
> 
> Okay, now, still more question, what, other than the 133 MHz Cyrix 6x86 chip,
> does IBM fab on its CMOS5X process? (.31 um effective channel length)

Probably PPC.  IBM will be officially announcing CMOS 6 process this year
(.20 um effective channel length).  Of course all this is total meanless.
It's how fast and cheap you can make a CPU that really counts and I feel IBM
has a strong edge with their design/process.

The P6 is a bloated pig and Intel's just throwing more silicon to keep from
falling behind (i.e. 604's 3.6 million transistors to 5.5 million in the P6.)
And that's not including the internal 256K/512K L2 cache. (512K in the 200 mHz
P6) 

x86 archtecture peaked with the P5 and heading into it's twilight years with
P6. The P7 will probably be a joke... Intel's supposely working on two versions,
one of which they are working with HP (which will handle PA-RISC and X86
instructions) and one that is being developed internally and handles x86
instructions only.

As far I can tell, VLIW will probably end up being software/hardware scheduling
system. Software hinting the direction of branches/resolving dependencies and
hardware making the final decisison at run time.  Not too much difference from
the current state of affairs with compilers for superscalar CPU, I'd imagine.

If they acheive their 2 billion ops/sec goal it will likely come from higher clock
speed than anthing else.  I think Intel and HP are only working together to "borrow"
some technologies to improve their own respective CPU designs.

That's my opinion anyways.