🚀 go-pugleaf

Tae Song (tsong@erols.com) wrote:
: David T. Wang wrote:
: > 
: > Okay, now, still more question, what, other than the 133 MHz Cyrix 6x86 chip,
: > does IBM fab on its CMOS5X process? (.31 um effective channel length)

: Probably PPC.  IBM will be officially announcing CMOS 6 process this year
: (.20 um effective channel length).  Of course all this is total meanless.
: It's how fast and cheap you can make a CPU that really counts and I feel IBM
: has a strong edge with their design/process.

Apparently not the PPC, with the possible excepion of PPC604@150 and the 
PPC601+.  I honestly don't believe that any PPC will be fabbed on that
.2 um process mentioned above, but it has been bounced around that
the upcoming PPC604e's will be fabbed on the .25 micron process.  IBM
still have an edge with the process technology, but they don't have any
significant volume with the bleeding edge process technology. 

: The P6 is a bloated pig and Intel's just throwing more silicon to keep from
: falling behind (i.e. 604's 3.6 million transistors to 5.5 million in the P6.)
: And that's not including the internal 256K/512K L2 cache. (512K in the 200 mHz
: P6) 

Sorry, I'd have to disagree (naturally) There is no P6 with the 512K cache 
at this time. the only announced "512K" version is the 166 MHz version, 
for the server market, though that version still hasn't shipped yet (to my
knowledge)  P6 does have a lot of transistors, but I don't think that 
you'll hear many people call the Dec Alpha 21164 bloated. it's got 9.3
million transistors on the same die.  Die size wise, the 200 MHz P6 is
smaller than PPC604-100, 120 and 133 (194 mm^2 vs 196 mm^2)

: x86 archtecture peaked with the P5 and heading into it's twilight years with
: P6. The P7 will probably be a joke... Intel's supposely working on two versions,
: one of which they are working with HP (which will handle PA-RISC and X86
: instructions) and one that is being developed internally and handles x86
: instructions only.

You are quite mistaken, there is no such thing as a 64 bit x86 instruction.
(not counting MMX ofcourse) Intel's version will indeed "handle" the 
newer 64 bit ISA.  Will the Intel chip handle PA-RISC? I don't know,
I haven't seen anything leak out on this subject. 

: As far I can tell, VLIW will probably end up being software/hardware scheduling
: system. Software hinting the direction of branches/resolving dependencies and
: hardware making the final decisison at run time.  Not too much difference from
: the current state of affairs with compilers for superscalar CPU, I'd imagine.

possibly, the papers I've read on VLIW suggest that it'll be difficult to scale
in the conventional manner we've been familiar with.  However, Intel/HP has
already stated that the P7 will be "Post RISC and Post VLIW"  So, it won't 
be any classical VLIW or RISC design (what the post thing means, I have no idea)
What I do know is that if someone wants to build a classical VLIW machine,
some of the scalability problems  could be solved with dynamic recompilers,
which could be built into the OS, so it's not an impossible task. So what's
the advantage you may ask? well, if we do get the advertised speedup, then
a new OS with a dynamic recompiler would be worth the trouble. (OTOH, if
the speedup isn't any better than a Dec Alpha per se, it'll be just a lot of 
hooey)

: If they acheive their 2 billion ops/sec goal it will likely come from higher clock
: speed than anthing else.  I think Intel and HP are only working together to "borrow"
: some technologies to improve their own respective CPU designs.

: That's my opinion anyways.

yes, "borrow".  However, everyone "borrows" from someone else. It has been
pointed out that all the "new" concepts contained in P6, like Out of Order 
execution, are all concepts that mainframe designers employed a good 20 to 30 
year ago.  Even VLIW is a good 20 years old.  The difficulty is in deciding
which technology to "borrow" and implement a state of the art CPU.