🚀 go-pugleaf

bouldin@enh.nist.gov (Charles Bouldin) wrote:

> Maybe. You forgot YIELD. Nobody knows the relative yields on 604 vs P5.
> Conventional wisdom is that yields are supposed to be higher on RISC
> chips?

There is no reason to assume that defects/square inch on a wafer
care about instruction sets.

> I am no process engineer, so perhaps someone who is can provide some real
> information. We sure aren't gonna find out from the companies...it's
> information that they don't reveal. The only thing that I think can be
> said fairly safely is that P6 yields are probably a LOT lower than P5 or
> 604...it can't be easy to get that huge full speed cache working on every
> chip.

The CPU and the cache in the PP are two separate chips, even when
they are mounted on the same chip carrier. ( But since the number
of available transistors on a chip doubles every 18 months or so,
prediction of the single chip PPro arrival date is left as an
exercise to the reader.)

Gerhard