🚀 go-pugleaf

In article <1991Feb1.153112.14717@linus.mitre.org> tomg@chance.mitre.org (Tom Gerasch) writes:

>I have been told that the 128KB cache that each processor has on
>the Symmetry is used only for data, that instructions are not cached.

This is incorrect.  The cache does not know one part of the *process*
address space from another.  All references to memory during normal
system execution (*) are made "through" the cache.  (*) Standalone
diagnostic software, etc, can disable the cache for test purposes.

>I would think that the movement of instructions over the bus when one
>has a medium to large Symmetry configuration would tend to saturate
>the bus.

Perhaps this would be a problem if in fact instructions were not cached.
However, they are.

>If the caches hold instructions as well as data, is there any way for
>the programmer to control the percentage of cache allocated for each?

No, because it is a physical cache.  That is, each physical address
in main memory maps to particular location (actually two, because the
cache is two-way-set-associative) in the cache; this is not under
programmer control.

>I would also appreciate any information on how Sequent makes use of the
>Intel code and data segment descriptors.

Segment descriptors are set at system initialization and never changed.
The paging unit in the i386/i486 is used to provide protection and
process isolation; page tables are manipulated at context switch time,
but segment tables are not.  This design was chosen for a variety of
reasons, particularly performance.
-- 
Jeff Berkowitz N6QOM	  uunet!sequent!jjb
Sequent Computer Systems  jjb@sequent.com