Article View: comp.sys.sequent
Article #791interrupt handling on the Symmetry system
From: George Bier
Date: Mon, 27 Mar 1989 17:47
Date: Mon, 27 Mar 1989 17:47
16 lines
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1123 bytes
I am hoping someone could enlighten me on how a processor is selected for
handling interrupts on a Symmetry system. I believe that on the Balance
system, the SLIC interface was used to select the processor currently running
the lowest priority process. What is done on the newer machines? In
addition, if you happen to know how other multiprocessors systems besides
the Symmetry (for example Alliants) select the processor to handle an
interrupt, I would appreciate hearing about that too. Any references
would also be appreciated.
thanks,
--george
Internet: bier@cs.wisc.edu
UUCP: ...!{harvard,seismo,topaz,akgua,allegra,usbvax}!uwvax!bier
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arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!rutgers!ucsd!ames!ncar!tank!uwvax!cottage!bierShow Full Headers
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!rutgers!ucsd!ames!ncar!tank!uwvax!cottage!bier From: bier@cottage.cs.wisc.edu (George Bier) Newsgroups: comp.sys.sequent Subject: interrupt handling on the Symmetry system Message-ID: <7367@spool.cs.wisc.edu> Date: 27 Mar 89 17:47:34 GMT Sender: news@spool.cs.wisc.edu Reply-To: bier@cottage.cs.wisc.edu (George Bier) Organization: U of Wisconsin CS Dept Lines: 16