Article View: comp.sys.sequent
Article #793Re: interrupt handling on the Symmetry system
From: Phil Hochstetler
Date: Tue, 28 Mar 1989 16:57
Date: Tue, 28 Mar 1989 16:57
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In article <7367@spool.cs.wisc.edu> bier@cottage.cs.wisc.edu (George Bier) writes: | | I am hoping someone could enlighten me on how a processor is selected for | handling interrupts on a Symmetry system. I believe that on the Balance | system, the SLIC interface was used to select the processor currently running | the lowest priority process. What is done on the newer machines? In | addition, if you happen to know how other multiprocessors systems besides | the Symmetry (for example Alliants) select the processor to handle an | interrupt, I would appreciate hearing about that too. Any references | would also be appreciated. SYMMETRY systems use the same mechanism as the BALANCE system does in regards to handling interrupts. The biggest performance changes are from using the 386 at a higher clock rate instead of the 32032, copy back cache, and going to memory based locks (instead of the SLIC). Phil Hochstetler UUCP: uunet!sequent!phil Sequent Computer Systems Beaverton, Oregon
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arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ukma!xanth!lll-winken!uunet!tektronix!sequent!philReferences:
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ukma!xanth!lll-winken!uunet!tektronix!sequent!phil From: phil@sequent.UUCP (Phil Hochstetler) Newsgroups: comp.sys.sequent Subject: Re: interrupt handling on the Symmetry system Message-ID: <13387@sequent.UUCP> Date: 28 Mar 89 16:57:08 GMT References: <7367@spool.cs.wisc.edu> Reply-To: phil@crg2.UUCP (Phil Hochstetler) Organization: Sequent Computer Systems, Inc Lines: 19