🚀 go-pugleaf

In article <18471@autodesk.COM> marc@autodesk.com writes:
|
|In article 51917@seismo.CSS.GOV, dsc@seismo.CSS.GOV (taste is the enemy 
|of art) writes:
|
|>Model	    SPECint92	SPECfp92	MIPS	MFLOPS	Cache*	Contexts
|>-----	    ---------	--------	----	------	------	--------
|>IPX	    21.8	21.5		28.5	4.2	64	8
|>2	    21.8	22.8		28.5	4.2	64	16
|>Classic    26.4	21.0		59.1	4.6	6	64
|>LX	    26.4	21.0		59.1	4.6	6	64
|>
|>* in KBs - cache is unified unless marked as data/instruction.
|
|Take careful note of the cache size on the Classic/LX.  One thing that 
|has been become obvious to us here is that the IPX and SS2 perform
|significantly better (in some case 2 or 3 times) on large programs with
|poor cache locality.  Benchmarks don't always tell the whole story...

One other thing to note is that the Classic and LX have a faster path to
main memory than the SPARCstation 2 so they should be able to live with a
smaller cache. The Classic/LX use 60ns SIMMs and pull 64bits at a time
from two 32bit SIMMs which means that it accesses memory more than twice
as fast as an SS2 (80ns 32bit). From a talk at the UK Unix User Group/ Sun
UK User Group New Year conference (1993) I found out that the SPARCstation 2
takes 25 clock cycles to fetch from main memory when it has a chache
miss! The Classic with its Tsunami chipset (a much nicer name than MicroSPARC
IMHO) doesn't have such a large miss penalty.

Looking at the figures above I would say that the SPECfp92 benchmarks
are unlikely to fit in a 6kbyte cache so comparing the SS2 and Classic
by the SPECfp92 numbers should give you quite a good comparison.

-- 
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Phillip Fayers                            JANET    : fayers@uk.ac.cardiff
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