🚀 go-pugleaf

AKONSTAM@TRINITY.BITNET (AARON KONSTAM) writes:
>b. RISC machines are however much slower in doing things like floating
>point instructions so they cheat and have floating point coprocessors to
>do the floating point arithmetic.

Slower?  Not necessarily.  The MIPS R2010 and R3010 VLSI FP coprocessors
execute an add in two cycles, a multiply in four or five cycles, and a
divide in 12-19 cycles.  The R3010 has a 40 nsec cycle.  These
coprocessors are pipelined and can concurrently execute multiple fp
instructions (with some constraints).  Other RISC architectures are
similar.

Cheating?  There are at least two obvious advantages of using a
coprocessor: you double the size of the available silicon for a given
level of integration, and you make it potentially easier to design a
functional unit which can execute in parallel with the main processor.

>d. Each process is given a register window for its local variables.  These
>widows are made to overlap so that a calling process shares resgisters
>with the process it calls. By means of these shared registers arguments
>are passed between the processes (or really not passed so calls are
>executed faster).  Ther is more to be said about this but I hope this is
>helpfull.

This is a description of a Register Window architecture, which is not
universal among RISC implementations.  For example, SPARC uses Register
Windows, MIPS doesn't.  There are advantages and disadvantages to Register
Windows, some architectural and some implementational.

John Hawkes    DISCLAIMER: <generic disclaimer, what do I know anyway, etc>
{ames,decwrl,prls,pyramid}!mips!hawkes  OR  hawkes@mips.com