🚀 go-pugleaf

In article <6392@amelia.nas.nasa.gov> yamo@wk46..nas.nasa.gov (Michael Yamasaki) writes:

   In article <56754@bbn.BBN.COM> lkaplan@BBN.COM (Larry Kaplan) writes:
   >
   >There are some true "killer micros" that address I/O issues on the market
   >right now.  BBN's newer "Butterfly" machine (TC2000) can be configured with
   >one I/O bus (read VME) for about every TWO processors.
   > [...]
   >These busses communicate with memory at a peak of 8 Mbytes/sec.  
   > [...]
   >One existing customer has 9 disks on five I/O busses.
   >

   Combined peaks of these five I/O busses is somewhat less than a single
   HPPI interface, less than half of an HSX (at 100 MBytes/sec.). Again,
   the numbers I used for the Cray 2 were for a typical single processor job
   with 50 or so other users on the system.

   >This amount of I/O is starting to look reasonable for a killer micro.
   >Some work remains to be done, however, in getting the software to effectively
   >use all of the bandwidth.
   >

   (an exersize for the reader? ;-)  Really, this doesn't seem like a trivial
   problem to me.

Let me agree completely.  I/O subsystem hardware is hard to do.  I've
just helped design an I/O subsystem with a peak 400mb/s aggragate rate
across 4 100 mb/s channels.  It required 10ns clocks and ECL logic and
a lot of wires.  It isn't going to be available on a killer micro (;-)
Once the hardware tradeoffs were made to get a working design, the
software was also hard.  This system required multiple cpus and
several memory to memory transfers (mostly between fifo's at interface
translators.  To avoid latency transfers had to be minimized,
requiring a lot of short circuting and duplicate state machine
management on both sides of the interface.  Latency requirements also
demanded that as much overlap as possible be provided in I/O
operations.  Doable, but not an exercise for the reader.


--
Martin Fouts

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If you can find an opinion in my posting, please let me know.
I don't have opinions, only misconceptions.