🚀 go-pugleaf

In article <1992Dec11.015624.15139@news.arc.nasa.gov> lamaster@pioneer.arc.nasa.gov (Hugh LaMaster) writes:
>In article <1992Dec10.225326.18139@nas.nasa.gov>, eugene@wilbur.nas.nasa.gov (Eugene N. Miya) writes:
>|> In article <1992Dec10.164402.17832@news.eng.convex.com>
>|> dodson@convex.COM (Dave Dodson) writes:
>|> >The oil industry consumes lots of supercomputer cycles doing seismic
>|> >analysis, and 32 bits is more than enough precision for that.  After
>|> >all, the seismic data has only 2 or 3 significant digits.  Using more
>|> >than 32 bits doesn't improve their ability to find oil.
>|> People think that if you double precision, all computations (adds, multiplies)
>|> double in time. They forget their long hand multiplications.  That's
>|> real estate.  Just another storage vs. time tradeoff.  Remember that you
>|> can gain insight by asking a person how many bits "single-precision" is.
>
>I don't know if this was discussed at SC '92, but at SC '91, several 
>presentations mentioned that (please read carefully) 64 bits will not
>be enough for some (significant) algorithms when the problem *sizes* are 
>scaled up to *TeraFLOPS* computing.  Therefore (please read carefully)
>microprocessor designs should now include some minimal support for
>128 bit FP so that the speed penalty is not enormous (full speed NOT
>required; 4:1 might be OK, 100:1 probably not).  
>
>Why should today's MFLOPS-speed uP's worry about TeraFLOPS problems?  
>Some of these micros are going to be used in MPP's.   This does not mean 
>that we can expect (many) people to use (or need) 128 bit FP in 
>their workstation-based computations.  But, generic uP's are becoming key 
>components in some MPPs, and, as uP's approach GFLOPS speeds, people will
>have to worry about this.  [And, for the same reason, micros need 64 bit
>addressing, even though most workstations are not going to exceed a 1 GByte
>of physical memory for a few years.]

I don't follow the logic here. Since when MPP usage has been an
important factor in uP design? I wouldn't hold my breath to see 128
bit FP in a uP. It may happen in the future, but only when desktop
machine users require  it. As far as uP's are concerned x86
style FP operations should satisfy almost everybody. Ofcourse current
implemetation is microcoded but I expect to see a hardwired
add/multiply unit soon. x86 provides 80 bit "extended precision"
registers to handle 64 bit IEEE standard operations. Register to
register operations are 80 bits and some C compilers support this
precision. I don't think 80 bit operations are IEEE. 

I don't think there is a good precision vs speed type tradeoff in a
pipelined FPU. If the hardware handles X bits per cycle, doing 2X
precision with pipelining would be pain. Think of all the flags and
exception detection for concurrently executing instructions. Designing
hardware to do this correctly can be harder than implementing 2X
precision for a scalar processor. When a 2X precision instruction is
provided in assembly language, you will end up executing it pretty
much on its own, with not much of pipelining. The bottom line is when
you have a pipeline unit you can either do 2X precision in about the
same time as X precision or much  slower. Ofcourse if you can get a
single cycle X precision FPU, then doubling your precision won't cost
too much (1:4 maybe). But still there is no "twice the precision half
the performance" type tradeoff for a generic uP. 


--
Sadun Anik, U of Illinois at Urbana-Champaign
Center for Reliable and High-performance Computing
e-mail: anik@crhc.uiuc.edu