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6 total messages Started by ICRJP Tue, 07 Apr 1992 16:53
New hitachi machine and claims
#54
Author: ICRJP
Date: Tue, 07 Apr 1992 16:53
5 lines
600 bytes
    I saw a small blip in the business news about Hitachi annoucing a new
machine.  Seems like they claimed a max of 35 gflops.  Anyone have some
specifics?

                                         rpalmer@dz.inre.asu.edu
Re: New hitachi machine and claims
#55
Author: OYANAGI Yoshio
Date: Wed, 08 Apr 1992 02:34
118 lines
4665 bytes
In article <92098.095338ICRJP@ASUACAD.BITNET> ICRJP@ASUACAD.BITNET writes:

 >Date: 7 Apr 92 16:53:37 GMT
 >Organization: Arizona State University
 >Lines: 6

 >    I saw a small blip in the business news about Hitachi annoucing a new
 >machine.  Seems like they claimed a max of 35 gflops.  Anyone have some
 >specifics?
 >					   rpalmer@dz.inre.asu.edu

 Here is a summary from the catalogue.  The price is not mentioned.
 The nominal theoretical peak is 32 GFlops not 35.  The information
 is translated inofficially from Japanese by the present poster.
 No guarantee of the correctness of the translation.  I post it
 for your information only.

 Yoshio Oyanagi
 -------------------------------------------------------------------------------

Hitachi's New Vector Supercomputer

On March 31, 1992, Hitachi Ltd. announced new series of vector 
supercomputers, HITAC S-3800 and HITAC S-3600.  S-3800 can consitute 
a multiprocessor system and the pipeline pitch is estimated to be 2 nano
seconds.  These are the third generation of HITAC supercomputers, 
following HITAC S-810 and S-820.  For the first time in Hitachi super-
computers, they support OSF (unix) operating system.
	(This paragraph is my comment, not from the catalogue.)

S-3800 has six models: 160, 180, 182, 260, 280, 480.  The first digit
shows the number of processors, the second the speed and the last
digit 2 shows that the system has two scalar units in one processor.  
The specification is as follows

Model:		      160     180     182     260     280     480
Max performance (GFlops)4	8	8	8      16      32
#scalar units	  	1	1	2	2	2	4
#vector units	  	1   	1	1	2	2	4
	(Hitachi calls scalar/vector processors instead of units.)

Instruction Processor
  #vector instructions                     99
  buffer memory(kB)   256     256   256x2   256x2   256x2   256x4
  #add+mult pipes	4	8	8	8      16      32
  #div pipes		1	1	1	2	2	4
  #mask pipes		1	1	1	2	2	4
  #load pipes		2	4	4	4	8      16
  #load/store pipes	2	4	4	4	8      16

Main Storage
  MB 		      256     512     512     512    1024    1024
		      512    1024    1024    1024    2048    2048
		     1024
  error check		1 bit correction, 2 bit detection

Extended Storage
  Max(GB)	       16      16      16      32      32      32
  Max transfer GB/s	                 2 or 4
  error check             	  2 bit correction

IO Processor
 		  0-64/128 optical channels. 32-64/128 metal channels.
		  Total channel through put: max 1.1 GB/s
		  BLMPX and BYMPX channels

Cooling					water
Facilities 	  Video output (NTSC and HDTV), HIPPI


S-3600 is an air-cooled supercomputer.  It has four models:

Models		     	      120     140     160     180
Max performance(GFlops)	      0.25    0.5	1	2
#scalar units			1	1	1	1
#vector units			1	1	1	1

Instruction Processor
  #vector instructions			    90
  Buffer storage			   256kB
  #add pipes			1	1	2	4	
  #add/mult pipes		1	1	2	4	
  #div pipes			1	1	1	1	
  #mask pipes			1	1	1	1
  #load pipes			0	1	2	4	
  #load/store pipes		1	1	2	4

Main storage
  MB			      128     256     256     512
			      256     512     512    1024
  error check	          1 bit correction, 2 bit detection

Extended storage
  max GB			6      16      16      16
  max transfer rate                   1 or 2 GB/s
  error check                      2 bit correction

IO Processor          0-64 optical channels and 16-64 metal channels
  total through-put                  max 288 MB/s
  
Cooling                                  air
Facilities                         Video(NTSC), HIPPI


The technologies of S-3800 is
  logic LSI:  25k gates, delay 60 ps and
              12k gates, delay 70 ps.

  vector register:  9k gates + 18 Kbit memory

  memory LSI: 11k gates+256kbits  and
               2k gates+64kbits.

Two kinds of operating systems:
  HI-OSF/1-MJ(Unix)  and VOS3/AS(MVS-like).
------------------------------------------------------------------------------

	         
Re: New hitachi machine and claims
#56
Author: Jason W Solinsky
Date: Wed, 08 Apr 1992 04:46
8 lines
1042 bytes
Supposedly, Hitachi has got their hands on a process that sucks wind except for
the fact that it has a 0.3 micrometer effective channel length. Apparently,
they've used this to put two full scale microprocessors on a single chip. From
what I've heard, the whole idea behind the product and everything else, was to
invest large amounts into scaling channel length down quickly, and then market
the technology quickly into the technological gap it creates in the market place.

Jason W. Solinsky
PLEASE IGNORE MY LAST POST
#57
Author: Jason W Solinsky
Date: Wed, 08 Apr 1992 04:49
4 lines
651 bytes
It seems I was refering to a different product that I had heard about. Not the
one in question.

Jason W. Solinsky
Re: PLEASE IGNORE MY LAST POST
#59
Author: Clark L. Coleman
Date: Wed, 08 Apr 1992 13:58
12 lines
1100 bytes
In article <1992Apr8.044927.24445@athena.mit.edu> solman@athena.mit.edu (Jason W Solinsky) writes:
>It seems I was refering to a different product that I had heard about. Not the
>one in question.


Not only that, the chip to which you referred was done by Fujitsu, not Hitachi.
And it is not part of any commercially available product, nor will it be soon,
if ever.
-- 
-----------------------------------------------------------------------------
"It is seldom that any liberty is lost all at once." David Hume
|||  clc5q@virginia.edu (Clark L. Coleman)
Re: PLEASE IGNORE MY LAST POST (Fujitsu VPU)
#71
Author: Craig Lund
Date: Wed, 15 Apr 1992 01:29
24 lines
1543 bytes
I missed the mail message that started this message chain.  However, looking
at the reply, I guess that someone referred to Fujitsu's VPU, which was
discussed in a paper at ISSCC in February.

If so, the reply is wrong.  Fujitsu is quietly selling the chip.  Fujitsu
will announce the first design wins at Supercomputing '92 Japan next week.

The VPU is a 289 MFLOP single chip vector unit implemented in .5 micron
CMOS.  The chip draws 5 watts at 3.3 volts.  It is a subset of the
VP2000.  The VPU sits next to any microprocessor.  So far, most of the
design wins sit next to SPARC's.

I know all this because I am a consultant that Fujitsu hired to provide
English language technical support (most of the design wins are in the 
U. S. and the U. K.).  I am also coordinating the various software
vendors.

I am just about to go to Japan to prepare for the trade show.  However,
if anyone wants to know more about the VPU, please send me mail.

Craig Lund
clund@chpc.org (another client)
NH Office +1 603 868 2300
NH Fax +1 603 868 5300
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