🚀 go-pugleaf

> Will it really be a 100MIPs,
> 100Mb/link processor?
> Will those of us who stuck by transputers in the
> face of increasingly fast competition be vindicated?

100MIPs: more than 150 claimed, and more than 20 MFLOPS (from tests of early
silicon). I think, though, that Inmos are still talking about 100MIPS and
10MFLOPS as realistic speeds for the first generation of these devices that will
be marketed.

100Mb/link -  Inmos claim 80Mbytes/second total throughput on all four links,
which is of the same order as your figure.

Vindication: that depends on why you stuck by transputers.  It won't be "the
fastest chip in the world" in the way that the T800 was (momentarily).

It will have slightly better support for operating systems and memory management
than the T8, but probably not as much as everybody would like. Inmos refer to
this as "an enhanced process model".  I doubt whether it will include memory
protection and virtual memory support.

It will nevertheless be very fast, with a much better balance of processing,
transfer and communication-set-up speeds than any other chip, so it will have
the edge in large-scale parallelism.  It will retain the support for real-time
and concurrent systems, still unmatched by other chips.  It will still be
excellent for embedded systems - but for many such purposes the T2, T4 or T8
will continue to be the best choice, being simpler and cheaper.

It will have 16Kbytes of on-chip memory, used by default as a cache but usable
directly as RAM if you prefer.

The links will not be directly compatible with T-series links (there will be
separate chips to interface the two kinds if required).  This is because they
will offer very important new facilities: multiple channels in each direction
supported on a single link (i.e., there will be a firmware
multiplexer/demultiplexer), and hardware through-routing so that channels can
connect processes on Transputers which are not directly connected. This is
achieved by wormhole routing, using a separate chip, which maintains the strict
occam model of communication - i.e., termination of transmission implies that
the whole message has been received.

Thus the typical complement of chips in system using H-series transputers will
include Transputers themselves and the new router chips, just as with T-series
processors you usually needed C004 switch chips (or equivalent).  Single-purpose
systems of moderate size may be able to do without the router chips, in the same
way that they might not have needed C004s if built with T-transputers. T-to-H
link adapter chips are likely to find a lot of uses, (a) in upgrading existing
systems, and (b) where it would be wasteful to use H-series chips for all
purposes in a system when a T4 or T2 can do many jobs so cheaply.

If you just want to use multiple-channels-per-link without through-routing
of messages, then the H-series links can do that without any external chips.

Personally, I have high hopes of this.  As much as anything else, its success
depends on Inmos' new openness to giving full support to the languages and
systems which potential customers want to use - C and Fortran and so on.

    John Wexler
    Edinburgh Parallel Computing Centre
_________________________________________________________________________________

Disclaimer: I am not an employee of Inmos, and Inmos has not certified or
approved what I have told you. It is fairly old information.  It may be
inaccurate, misleading, out-of-date, or just plain wrong. I may have remembered
some of it wrongly or incompletely. I got it all from (a) published, widely
available, sources, and (b) Inmos statements given freely, publicly, and without
any request for confidentiality. Neither I nor the University of Edinburgh will
be responsible for any use you make of this. No commitment can be assumed for
Inmos to deliver any of the specifics that I have described.