Transputer Reset

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#1046

From: Kevin James Bertram
Date: Mon, 15 Oct 1990 23:21

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	It's been a week since I had asked if the ERROROUT signal
of the Transputer is cleared on reset. Unfortunatly there were no
answers. I'll rephrase the question in hope of an answer.

	Does a reset sequence clear the ERROROUT signal (appears on
pin 1D of a PGA package) and also the ERROR flag within the CPU?

The reset pulse that appears on pin 3E follows a low-high-low transistion
with a duration of about 300 ms. ERRORIN (if supplied on the chip) on pin
3D is low, ANALYSE is low (pin 2F). The CPU type can be anyone of the
Transputers available.

	-Kevin (kevin@latcs1.oz)

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Path: arc1-ca.pugleaf.net!utzoo!attcan!uunet!munnari.oz.au!mel.dit.csiro.au!latcs1!kevin
From: kevin@latcs1.oz.au (Kevin James Bertram)
Newsgroups: comp.sys.transputer
Subject: Transputer Reset
Keywords: reset
Message-ID: <9006@latcs1.oz.au>
Date: 15 Oct 90 23:21:21 GMT
Organization: Comp Sci, La Trobe Uni, Australia
Lines: 14