🚀 go-pugleaf

In article <1110.9102261633@inmos-c.inmos.com> RABAGLIATIA@isnet.inmos.com
(ANDY RABAGLIATI) writes a list of transputer variants.

Here I add some extra information.

    This is the list of Transputer variants, and their respective
    instruction sets.

                  T212 T222 T225 T400 T414 T425 T800 T801 T805

    Memory Kbytes   2    4    4    2    2    4    4    4    4
    T4 Float P.                    X    X    X
    T8 Float P.                                   X    X    X
    2-D Blk Move                   X         X    X    X    X
    Breakpoint                X    X         X         X    X
    TPID A rev      X    X   40   50    X   00    X   20   10

    FMUL                           X    X    X    X    X    X
    DUP/WSUBDB                X    X         X    X    X    X
    CRC/BITCOUNT              X    X         X    X    X    X
    FPTESTERR                      *         *    X    X    X

    Bytes per word  2    2    2    4    4    4    4    4    4
    MemStart(words)18   18   18   28   18   28   28   28   28
    MemStart(hex) %24  %24  %24  %70  %48  %70  %70  %70  %70

    The TPID numbering scheme allows for 10 revisions. Thus the T400B
    is 51. (Actually, the T400A was a quick hack of a T425, so it
    has a T425 TPID).  T212, T222 and T414 all do nothing when executing
    LDDEVID.  T800 pops C into B and trashes A.
    (It was a retro-fitted instruction!)

    The FPTESTERR instruction returns TRUE (meaning the FPU flag wasn't set)
    on the T425 and T400 transputers. This means that the same bootstrap
    can be used as on the T8 series, where this instruction is used to clear
    the FPU error flag.

    MemStart - the notation %hh means that this hex value should be added
    to MOSTNEG INT. EG. on a T414 %48 means #80000048.

---
Conor O'Neill, Software Group, INMOS Ltd., UK.
UK: conor@inmos.co.uk		US: conor@inmos.com
"It's state-of-the-art" "But it doesn't work!" "That is the state-of-the-art".