🚀 go-pugleaf

in article <6048@lanl.gov>, jxdl@lanl.gov (Jerry DeLapp) says:
> Summary: Cheap, fast, powerful, cheap, cheap, (I like cheap)


> The transputer is fast (about the equivalent of a vax or sun 3 now,
> and getting faster).

The comparison was with a 68030 or 80386, not a vanilla 68000.  For
integer processing speed, a 68000 isn't quite a VAX 750.  The only
T800's I've seen benchmarked IN A SYSTEM process integers in the
VAX 780-785 range, like a medium performance 68020 system (which is
just what a smaller Sun 3 is).  68030 systems outperform 8xxx VAXen
in most integer benchmarks.

> The communications are very fast, have very low startup overheads,
> and operate without any need of the CPU after setup.

Any DMA driven communications channel will operate without CPU 
intervention after setup.

> The (T800) transputer has on-chip floating-point support.

That's probably it's nicest feature.  The on-chip floating point i
pretty fast, though it's a small set of operations.  You'd have to
go to a Weitek chipset for that kind of performance on a 68xxx or
80xxx.  Motorola's 88100 has an even better on-chip floating point
scheme, using separate execution units for addition and multiplication.

> The context-switch time on a transputer makes the 68xxx look like
> a pig.

ONLY IF you can use the hardware defined task model.  In that case,
it's pretty nice, since it'll actually wait for a minimum of task
state before swapping.  If you wanted to run a standard operating
system on the thing, you'd be in trouble.  And the 68030's interface
to memory makes the T800's "look like a pig", to coin a phrase.

> The transputer is RISC technology. The small instruction set means
> that it's fairly easy to port compilers to it (although INMOS seems
> to be real stodgy about realizing that the real world wants C and
> FORTRAN).

The Transputer isn't RISC at all.  About the only thing it has in common
with true RISC-methods CPUs is that it's rather small.  There aren't
any registers; RISC chips typically have a minimum of 32, some close to
200.  A good portion of Transputer instructions are slow, microcoded
instructions; RISC chips use hardwired instructions that execute in or
near single cycles.  Transputers don't have cache memory; all RISC
chip COUNT on caches.  Transputers don't have memory management, which
is crucial to running protected operating systems.

I think if they get low cost enough, Transputers will make excellent
satillite controller in a 68xxx or similar system, what with the on-chip
RAM and math and all.  They're also well suited to certain kinds of 
parallel problems that lend themselves well to loose coupling.  Tim King's 
company Perihelion does offer a C compiler for the things that's not 
supposed to be all that bad; certainly more palatable to most software
people than Occam.  So I think Transputers have their place, but that
place isn't the place currently occupied by most CISC and RISC CPUs, that
of main processor.

> _    /| The opinions here are my own, and even I don't agree with me :-)
> \'o.O'  I am not an employee of LANL, I just use their computers.
> =(___)= I stole the .sig file, but I did not shoot no deputeeee.
>    U    Bill sez: AAAAK! PHHHT!   jxdl@lanl.gov
-- 
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