🚀 go-pugleaf

In article <8902281135.AA05126@uk.ac.ox.prg>
PVR%bgerug51.earn@NSS.CS.UCL.AC.UK (Patrick Van Renterghem / Transputer
Lab) writes:

>Long time ago, there was a discussion here about lowering the clock frequency
>(to 500 kHz e.g.) for minimizing the power consumption. Who remembers anything
>of that ? More precisely, I would like to know if it is possible (I think it is,
>playing around with DisablePLL and your own ClockIn) and if someone has tried
>it. With T800's of course.

Yes, this has been done.  Smith Associates (address below) developed a
fault-tolerant demonstrator system for SPACE applications (European
Space Research and Technology Centre (ESTEC) contract
6946/86/NL/PP(SC)).  The demonstrator ran some image compression stuff
and mission-critical satellite orientation control.  As a result of this
demonstrator, ESTEC is now developing a system to be launched on a
future University satellite (perhaps UOSAT3).  In this design, the clock
speeds of the transputers are reduced to conserve power (less than
half-a-wot per transputer module), and the system keeps going. 
Brilliant.

	For further information on this, you could contact

		Richard Armstrong,
		Smith Associates Ltd,
		Surrey Research Park,
		Guildford,
		Surrey GU2 5YP,
		ENGLAND.

		Tel (0483) 505565.

	Unfortunately, I don't have an email-id for this.

	Hope this is useful.

	Cheers,
		Andy Hamilton.

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