🚀 go-pugleaf

There's been a lot of "talk" recently about the H1.  What interests me is the
technical issues.  The link bandwidth of the H1 is reportedly to be
~80Mbytes/sec. Since the links will reportedly be running at ~100Mbits/sec, I
take this that it will have 8 links, each running at ~10Mbytes/sec. 

Now, one of the BIG advantages of using the transputer is that I/O can proceed
autonomously with the processor, and both links and processor share the same
common memory.  From the rough tests I've done, by comparing the timings of a
program and the same program with I/O occurring on a couple of the links,
there is only a few (1-2%) difference in the times, i.e. the second case will
only run about 1.5% faster if I/O wasn't happening. 

Now, consider the H1 with a bandwidth of 80Mbytes/sec.  If all (8?) links are
running flat out, and the same memory is being shared between the processor
and the links, will the processor be able to get a look into the memory or
will the links saturate the memory bandwidth? 

My feelings are that INMOS are probably up to some good stuff here if I/O will
only interfere with a program by a small amount.  Maybe they are buffering up 
data at the links?

Any comments from anyone?

Mark Edmonds
edmonds@uk.co.philips.prl