🚀 go-pugleaf

In article <8911282053.AA06866@tcgould.TN.CORNELL.EDU> STORZ@EMBL.BITNET writes:
>
>The information I have read (SGS-Thomson-Cheft Pistorio) announced
>the H1 as
>      - full command compatible to t4/t8 transputers (???)
>      - 100 MIPS/20 MFlops
>      - at least 18 months from now
>      - fighting for the embedded market
>
>        - virtual links (routing in hardware)
>        - internal RAM (used like before or switched as fast CACHE)
>        - commands for fast 'standard' languages like C
>        - (perhaps MMU ???)
>
>Clemens Storz
My sources (who will remain entirely anonymous) have stated the
following data:
 - 100 MIPS
 - 4 bi-directional links @ 10 MBytes/s per direction
 - virtual channels (potentially worm-hole thru-routing)
 - 15 MFlops Linpac
 - 30 - 50 MHz clock rate (Guess which clock for above figures)
 - 168 pins (maybe 144) 
 - 16 KByte on-chip fully associative cache
 - two external memory configurations selectable thru on-chip registers
   - SRAM - 20 bit address bus + 32 bit data bus
   - DRAM - 16 bit address bus (RAS/CAS multiplexing done on-chip)
          - 32 bit data bus
          - 4 banks of interleaved DRAM
          - each bank can be page mode or static column mode accessed
          - can directly drive up to 16 MBytes DRAM
 - improved interrupt handling
 - multiple priority levels?
 - instruction set compatible with existing transputers
-- 
Richard M. Stein (aka, Rick 'Transputer' Stein)
Sole proprietor of Rick's Software Toxic Waste Dump and Kitty Litter Co.
"You build 'em, we bury 'em." uucp: ...{spsd, zardoz, felix}!dhw68k!stein