🚀 go-pugleaf

I am attempting to implement a communications protocol using
transputers, and I think it it necessary to use some kind of error
detection in each packet.  My first choice is to use a 16-bit
checksum (ala UDP or TCP), but since transputers don't like 16-bit
quantities (and especially since a shift right by 16 bits takes 18
cycles), I turned to the transputer's "crcword" instruction.  So, I
need to provide a "generator" word (page 69, Compiler Writers' Guide).

Another book I have states that IEEE 802 uses CRC-32, which defines
the generator polynomial as:

1 + X + X^2 + X^4 + X^5 + X^7 + X^8 + X^10 + X^11 + X^12 + X^16 + X^22
+ X^23 + X^26 + X^32.

This is confusing to me, because this polynomial seems to be of order
33; i.e., if I were to set a bit in the generator word for each term
in the above polynomial, I would need a 33 bit word, not a 32 bit
word.  I must be very confused...  Does anyone out there understand
this stuff?

Or, alternatively, can anyone suggest a way to implement a 16-bit
checksum (or a 32-bit checksum) efficiently (i.e., without 16 shifts
per word)?

Or, do you think doing the 16 shifts will be faster than using the
crcword instruction?

Thanks.

Vic Norman