🚀 go-pugleaf

James Salsman (js7a+@andrew.cmu.edu) writes:

-STORZ@EMBL.BITNET writes:
->         - virtual links (routing in hardware)
-Yes.  Keeping this backward-compatible is going to require
-stressful contortions on the part of many designers...
-
->         - internal RAM (used like before or switched as fast CACHE)
-Only 2K instead of 4K.
-
->         - commands for fast 'standard' languages like C
-Dunno.  I sure hope they come up with somthing faster than
-the "lend" instruction for tight inner toops, though.
-
->         - (perhaps MMU ???)
-Yes, designed to run Unix.  Also static column mode DRAM addressing.
-
-> Somewhere else I heard about 6 links ?
-Nope, only TWO!!!  Kinda defeats the purpose.  The H-1 is
-definetly going to be a linear array.
-
-The funny thing is that it seems very much like the iWarp
-being developed here.  I'm soooo confused.


I'm afraid that James is mixing up information from two of our  
recent announcments. The T400 has two links and 2K of RAM  and 
is available now (it is a low-cost derivative of the T425). The
T400 is only available at 20MHz, in plastic packages and costs
$20 in volume. The T425 will still be available and will probably
follow the T805 to 30MHz clock speeds.

The other points basically come from the announcement of the H1 
programme. To clear things a little, here is the total information 
included in the foil on H1 used at recent customer seminars in the 
US and Japan:


                   H1 Transputer  

          Code compatible with T800
          100 integer MIPS
          20 MFLOPS                     
          Support for Operating Systems
          80Mbytes total link bandwidth                                                     
 

This is all the information INMOS has released on H1. Read it carefully !  

David Boreham, INMOS Limited | mail(uk): davidb@inmos.co.uk or ukc!inmos!davidb
Bristol,  England            |     (us): uunet!inmos.com!davidb
+44 454 616616 ex 547        | Internet: davidb@inmos.com