🚀 go-pugleaf

In article <8795@ganymede.inmos.co.uk> David Boreham writes:

>If you want to, mail me describing what you are
>thinking of doing and I'll see if there is another
>way, such as putting the device in PLL disable mode.

Sounds interesting. Could You explain this in details?

>>Does anybody know the specified phase relationship between the 5 MHz input
>>clock to the transputer and its ProcClockOut ? 
>There isn't one.

Even two transputers connected to the same 5 MHz oscillator have unpredictable
internal clock phases. Inmos does not specify a clock phase, so this os OK.
The link data transmission is specified as "asynchronous".
The "floating" phases of the PLLs between two transputers have the effect, that
the link speed may differ (max. 4% at 10 Mbit/s [1], 7.4% al 20 Mbit/s [2]).
I discovered this phenomena beacuse my link speed measurements changed from
day to day. Later I found out, the link speed may change after turning off
and on the power.
I guess there are two PLLs in every Transputer, one with 15..30 MHz for the
CPU and one with 100(?) MHz for the links.
The phase differences between these two or four PLLs in two transputers can
explain the different link speeds: depending on the phase of the clocks in
the sender and receiver link hardware, a received bit from an other transputer
may be recognized one clock earlier or later.

So the execution order of processes may change, and transputers are NOT
deterministic! Benchmarks with lots of communication may be unprecisely
(up to 7%).

References: (both in german, sorry)

[1] Dieter Homeister
Paralleles Booten von Transputern
in: Elektronik 5, March 1990

Karl Junk
Zufallseinfluesse auf die Linkuebertragungsgeschwindigkeit bei Transputern
in: 7. Entwicklerforum Transputer / Huttenloher,Fey (Ed.)
Munic, Oct. 1989

--------------
Dieter Homeister, Universitaet Stuttgart,
Institut fuer parallele und verteilte Hoechstleistungsrechner (IPVR)
7000 Stuttgart 1, Azenbergstr. 12, Tel 0711-121-1342, W-Germany
e-mail homeister@informatik.uni-stuttgart.dbp.de