🚀 go-pugleaf

tif@doorstop.austin.ibm.com (Paul Chamberlain) writes:

>Let's say I have source1.c, source2.c, and source3.c.  I want to
>be able to say "make exe1", "make exe2", or "make all".  But I
>want it to do the right thing if I say "make all; make all".  i.e.

>	cc -DDEF1 -c source1.c; cc -DDEF1 -c source2.c; cc -DDEF1 -c source3.c
>	cc -o exe1 source1.o source2.o source3.o
>	cc -DDEF2 -c source1.c; cc -DDEF2 -c source2.c; cc -DDEF2 -c source3.c
>	cc -o exe2 source1.o source2.o source3.o
>and then
>	`all' is up to date.

>[has 2 targets, same sources, different preprocessor definitions
>to produce different objects with the same names]

I would suggest that the object files (.o) be given different names
depending on the flags they were compiled with. Make gets confused
because it thinks that source1.o is the same as source1.o.

How about something like this:

all:	exe1 exe2

exe1:	source1.def1.o source2.def1.o source3.def1.o
	${CC} -o $@ source1.def1.o source2.def1.o source3.def1.o

exe2:	source1.def2.o source2.def2.o source3.def2.o
	${CC} -o $@ source1.def2.o source2.def2.o source3.def2.o

source1.def1.o:	source1.c
	${CC} -o source1.def1.o -DDEF1 -c $?

source2.def1.o:	source2.c
	${CC} -o source2.def1.o -DDEF1 -c $?

source3.def1.o:	source3.c
	${CC} -o source3.def1.o -DDEF1 -c $?

source1.def2.o:	source1.c
	${CC} -o source1.def2.o -DDEF2 -c $?

source2.def2.o:	source2.c
	${CC} -o source2.def2.o -DDEF2 -c $?

source3.def2.o:	source3.c
	${CC} -o source3.def2.o -DDEF2 -c $?


 ~!paul
--
Paul Ziemba  api!gpz  gpz@ESD.3com.com  408.764.5390   OS/2: just say no.

"How much char could a char star star if char star could star char?"
(quote stolen from mspercy@clemson.clemson.edu)