🚀 go-pugleaf

ellis@ultra.dec.com (David Ellis 15-Nov-1990 0915) writes:

>Consider a Makefile for an executable built from a large number of .o files, 
>each separately compiled from a .c file.

>If we use a single .c.o rule for compiling all the source files, then it 
>seems that a change in a .h file that is #include'd in a .c file will
>not be picked up by Make to automatically force recompilation of the .c file.

>One workaround is to replace the single .c.o rule with a collection of rules, 
>one for each .o file, listing the dependencies on the .h files #include'd in
>the corresponding .c file.  But this is a lot of writing, and if we change
>the "#include" lines in any .c file, we have to update the Makefile with the
>corresponding change.

>Is there a simpler way?
Yes - the simplest think to do is leave the single rules line in there
and then add the dependancy lines after:-

.c.o
	cc ....... 

foo.o: foo.c inc.h
bar.o: bar.c inc.h

This says that to make a .o from and .c do a cc on it AND that foo.o
depends both on foo.c and inc.h.

This works fine. However you must update the make to reflect the changes
in dependancy if you add another .h. There are dependancy makers around
- ie progs/scripts that scan the sources and build the rules but I have
never used them as it seems to me you can keep them up to date by hand.

>----
>David  J  Ellis
>Digital Equipment Corporation, Secure Systems Group 
>Mailstop LTN1-1/D07
>295 Foster Street, Littleton MA 01460
>(508) 486-6157
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>Internet: ellis@ultra.enet.dec.com